Abstract: Improved methods and apparatus for forming an assembly by attaching an electronic package to a substrate are disclosed. The electronic package includes a microelectronic device, conductive leads to couple the device to the substrate, and an encapsulant surrounding the device and a portion of the conductive leads. A filler is added to the assembly to surround the otherwise exposed portion of the leads. The filler material is selected such that the dielectric constant of the filler is approximately the same as the dielectric constant of the encapsulant. Surrounding the lead with material having substantially similar dielectric constants reduces impedance variation along the length of the lead.

Abstract: A system is disclosed for improving the quality of coded speech information in a communications system. The system dynamically determines pulse tracks that represent an excitation signal. A track or set of tracks that define possible pulse positions are determined based on available information sent to a decoder. Alternatively, at least one first track may include fixed pulse positions, and the remaining tracks may include dynamic pulse positions arranged according to the position of a coded pulse in the first track. Also, all tracks may include dynamically arranged pulse positions that are arranged according to a reference position that is likely to produce a high magnitude pulse signal.

Abstract: A Doherty amplifier system including a quarter wave transformer/combiner circuit which may be implemented as a low cost radio frequency integrated circuit, thereby absorbing and minimizing the effects of parasitics such as bond wires and stray capacitance. The quarter wave transformer/combiner circuit may be a lumped pi network configured as an integral number of sections coupled in parallel, with each such section comprising a series combination of a shunt inductance, series capacitance, and shunt inductance. The circuit may also provide bias voltage to the carrier and peaking amplifiers and/or maintain DC isolation therebetween. The circuit may also decrease the load impedance presented to the carrier amplifier as input power increases, thus allowing the efficiency of the system to be kept relatively constant over a prescribed power range.

Abstract: A method and apparatus for automating and controlling the programming operations in a flash memory is provided to enable a microcontroller to accomplish various other controlling tasks while the programming operations are being conducted. A state machine is provided for controlling a plurality of sequences utilized in programming the flash memory, with various functional circuits provided to facilitate the programming and verification of flash memory cells. In a preferred embodiment, the reprogramming of the flash cells is limited to those flash cells verified as a programming failure, thus reducing the necessary programming of the flash memory cells which may impede the ability to program those flash cells. The control system may also be configured to provide for automating and controlling the erasing operations in a flash memory. The common interface circuitry may be employed to facilitates automation and control of both programming and erasing functions.

Abstract: A modem system having two modem devices digitally connected to a digital telephone network includes an inband control signal channel. The inband control signal channel is formed by using the most significant bit position of every sixth transmitted codeword for the transmission of control data. The control signal includes a predetermined header section that is monitored by the receiving modem to maintain frame synchronization and to correct for digital frame slippage. The control signal also includes a number of control data packets that contain information related to the initiation of control procedures such as rate renegotiations and retraining requests. The disclosed inband transmission techniques may additionally (or alternatively) be utilized to define a secondary data channel.

Abstract: A typical integrated circuit device may include a central processing unit (CPU), trap and patch (T&P) logic circuits and registers. Volatile RAM and read only memory (ROM) are also provided. A predetermined number of memory locations in the RAM are allocated for defective memory cell replacement. When power is turned on or the system is reset, the CPU executes a program stored in ROM which identifies defective RAM locations on the fly and loads the trap and path circuits and registers with the defective addresses and the replacement or patch RAM locations (addresses). When the CPU reads or writes to the bad RAM locations, the T&P logic inserts the patch address of the good RAM memory location for the reading and writing operations. In this manner, virtual defective RAM replacement is transparent to the CPU.

Abstract: In one embodiment a precursor gas for growing a polycrystalline silicon-germanium region and a single crystal silicon-germanium region is supplied. The precursor gas can be, for example, GeH4. The polycrystalline silicon-germanium region can be, for example, a base contact in a heterojunction bipolar transistor while the single crystal silicon-germanium region can be, for example, a base in the heterojunction bipolar transistor. The polycrystalline silicon-germanium region can be grown in a mass controlled mode at a certain temperature and a certain pressure of the precursor gas while the single crystal silicon-germanium region can be grown, concurrently, in a kinetically controlled mode at the same temperature and the same pressure of the precursor gas. The disclosed embodiments result in controlling the growth of the polycrystalline silicon-germanium independent of the growth of the single crystal silicon-germanium.

Abstract: a communication device that includes a base. The base includes a line interface for receiving incoming communications over a network line and sending outgoing communications over the network line, a communication transceiver for interfacing the communication device over a communication link to other communication devices in a same in-home network and for interfacing other communication devices in the same in-home network to the line interface via the communication link, and a storage medium for storing communication software that allows the communication device to communicate with other communication devices through the transceiver. The communication device also includes a processor coupled to the storage medium and to the line interface. The processor is configured to run the communication software and to receive incoming communications through the line interface and to send an outgoing communications through the line interface. The communication transceiver can be a RF short range transceiver.

Abstract: According to various embodiments, a conductor is patterned in a dielectric. The conductor can be patterned, for example, in the shape of a square spiral. The conductor can comprise, for example, copper, aluminum, or copper-aluminum alloy. The dielectric can be, for example, silicon oxide or a low-k dielectric. Trenches are etched next to the patterned conductor in the dielectric. The trenches are filled with a material having a permeability substantially higher than the permeability of the dielectric. The high permeability material can be, for example, nickel, iron, nickel-iron alloy, or magnetic oxide. As a result, an inductor having a high inductance value is achieved without lowering the quality factor of the inductor.

Abstract: In a preferred embodiment, the invention uses an 8-to-1 data serialization circuit in the transmitter to convert 80-bit parallel 200 MHz data to 10-bit parallel 1.6 Mb/s date. On the receiver side, data are captured using a forwarded clock and de-serialized. A single global DLL generates 16 master phases without reference to the word boundaries of data being transmitted. These 16 unreferenced phases are input to a phase rotator that, via a series of calibration steps, maps the unreferenced phases into named phases, and in doing so references the phases to the word boundary of the data being transmitted over the slowest data line of the parallel channel. The named phases are then input to a data interpolator in each receiver, which generates 16 local phases. The 16 local phases correspond to the data-bit centers and data-bit edges for each of the 8 bits transferred per major channel clock period.

Abstract: A multi-pole surface acoustic wave filter in which one or more reflectors are inserted in a gap between source and destination interdigital transducers. The number of reflectors which are inserted bears a relationship to the number of poles in the filter frequency response.

Abstract: A communication system for communicating RF signals at any one of a plurality of communication standards through a common antenna is disclosed. The communication system comprises a transmitting unit, a receiving unit, an IF LO frequency generator, an RF LO frequency generator, a reference source, and an antenna. The transmitting unit has a transmit RF information signal output, a modulator for transforming a transmit baseband information signal into a modulated transmit IF information signal, and an upconverter for upconverting the transmit IF information signal into a transmit RF information signal.

Abstract: A preferred timing recovery scheme is particularly suitable for a high speed digital data communication system that employs T-spaced equalization in the receiving device, where echo cancellation occurs after equalization. The timing recovery technique is based upon an analysis of the impulse response of the equalizer structure (e.g., a structure having a feedforward equalizer and a decision feedback equalizer). The filter tap coefficients of the equalizer elements are analyzed and the sampling phase is adjusted such that a cost function associated with the performance of the equalizer structure is substantially optimized. The sampling phase of the receiver is adjusted in response to a control signal generated as a result of the timing recovery techniques.

Abstract: A traffic manager system is coupled to a communication system for scheduling transmission of data associated with a plurality of connections in the communication system. The traffic manager can include a schedule table, a global priority queue, and a scheduler. The schedule table includes a plurality of slot locations, each having a plurality of tunnel entries. The scheduler is coupled to the schedule table and the global priority queue. The global priority queue has a tunnel level associated with the plurality of tunnel entries of the slot. The scheduler processes the slot locations in the schedule table and sets a tunnel active in response to processing one of the plurality of tunnel entries.

Abstract: A modem system utilizes PCM encoding and transmission techniques in the upstream direction from a client modem (connected to a digital network via an analog loop) to a central site modem (connected to the digital network via a digital link). The modem system employs precoding techniques that enable the transmit signal to be pre-equalized to compensate for the analog channel characteristics. The precoding technique generates a plurality of equivalent signal point sequences in response to a digital data input. The signal point sequences are analyzed and compared relative to a predetermined cost metric such as transmit power. A preferred signal point sequence is selected and transmitted to the central site modem.

Abstract: A communication circuit includes a first transceiver circuit, a second transceiver circuit, and a transformer. The transformer includes a single core, an input coil, and first and second output coils. The input coil is configured to be coupled to a signal source. The first output coil is coupled to the first transceiver circuit, and the second output coil is coupled to the second transceiver circuit.

Abstract: A wireless transceiver comprises a digital to analog converter having an input for receiving a digital representation of a direct sequence spread spectrum signal and having an analog output. A bandpass or lowpass filter has an input coupled to the analog output of the digital to analog converter and has a filtered output. An adder has a first input coupled to the filtered output and a second input coupled to a loop control voltage generated by a phase lock loop. The adder produces a summed output. A VCO integrated into the phase lock loop has a control input coupled to the summed output. An RF output of the VCO produces a continuous phase frequency shift keyed spread spectrum signal in response to the digital representation of the direct sequence spread spectrums signal.

Abstract: A dual-mode wireless telephone which is capable of operating on two different bands of frequencies. The dual-mode telephone having a single phase lock loop combined with a single local oscillator that can select between two frequencies in two widely spread output frequency bands such as the bands in the GSM and DCS standards. A switch in the phase lock loop selectively swaps an UP signal and a DOWN signal to achieve either a high side lock or a low side lock. When the phase lock loop is high side locked, a target frequency in a higher band of output frequencies is generated. When the phase lock loop is low side locked, a target frequency in a lower band of output frequencies is generated.

Abstract: A system and method for providing a software trap and patch function to low power, cost conscious, and space constrained applications. When a programming error in a first memory is discovered, a data structure comprising a trap address, patch code, and patch address are stored in a second memory. A power-on-reset process detects the presence of the data structure, and in response thereto, enables the trap and patch function. In operation, upon the occurrence of a trap condition, the first memory is disconnected from the data bus and a predetermined instruction circuit is activated. Upon activation thereof, the predetermined instruction circuit, which comprises solely combinational circuitry, places the op code of the predetermined instruction on the data bus. In one embodiment, in which the predetermined instruction is a software interrupt instruction, a predetermined bit of the PSR is placed in a defined state responsive to the occurrence of a trap condition.

Abstract: Structure and method for fabrication of an improved capacitor are disclosed. In one embodiment, the disclosed capacitor includes a metal column comprising a number of interconnect metal segments and a number of via metal segments stacked on one another. The metal column constitutes one electrode of the capacitor. Another electrode of the capacitor is a metal wall surrounding the metal column. In one embodiment, the metal wall is fabricated from a number of interconnect metal structures and a number of via metal structures stacked on one another. In one embodiment, the metal wall is shaped as a hexagon. In this embodiment, a tight packing arrangement is achieved by packing individual hexagonal capacitors “wall to wall” so as to achieve a cluster of individual hexagonal capacitors. The cluster of individual capacitors acts as a single composite capacitor. In one embodiment, the interconnect metal and via metal are both made of copper.