Patents Assigned to Coval
  • Patent number: 9045691
    Abstract: The present invention relates to a ceramics composite including: a matrix phase including Al2O3 or a substance in which one selected from Sc2O3 and Ga2O3 is incorporated into Al2O3; a main phosphor phase formed in the matrix phase and including a substance represented by a general formula A3B5O12:Ce in which A is at least one selected from Y, Gd, Tb, Yb and Lu and B is at least one selected from Al, Ga and Sc; and a CeAl11O18 phase mixed in the matrix phase and the main phosphor phase.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: June 2, 2015
    Assignee: Covalent Materials Corporation
    Inventor: Masaki Irie
  • Patent number: 8940390
    Abstract: The present invention relates to a ceramics composite including an inorganic material which includes: a matrix phase including a translucent ceramics; and a phosphor phase including YAG containing Ce, in which a content of the phosphor phase is from 22% by volume to 55% by volume based on the whole phase including the matrix phase and the phosphor phase, a content of Ce in the YAG is 0.005 to 0.05 in terms of an atomic ratio of Ce to Y (Ce/Y), and the ceramics composite has a thickness in a light outgoing direction of 30 ?m to 200 ?m.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: January 27, 2015
    Assignee: Covalent Materials Corporation
    Inventors: Masaki Irie, Mitsuhiro Fujita
  • Publication number: 20140339679
    Abstract: A nitride semiconductor substrate suitable for a high withstand voltage power device is provided in which current collapse is controlled, while reducing leakage current. In a nitride semiconductor substrate, wherein a buffer layer, an active layer, and an electron supply layer, each comprising a group 13 nitride, are stacked one by one on a silicon single crystal substrate, the buffer layer has a structure where a multilayer stack in which a pair of nitride layers having different concentrations of Al or Ga are repeatedly deposited a plurality of times on an initial layer of AlxGa1-xN (0?x?1) is stacked, and includes a doping layer whose carbon concentration is 1×1018 to 1×1021 cm?3 and whose Si concentration is 1×1017 to 1×1020 cm?3, a thickness of the doping layer is 15% or more of the total thickness of the buffer layer.
    Type: Application
    Filed: May 7, 2014
    Publication date: November 20, 2014
    Applicant: Covalent Materials Corporation
    Inventors: Jun KOMIYAMA, Akira YOSHIDA, Hiroshi OISHI
  • Publication number: 20140255593
    Abstract: Applicants have disclosed a process for fusing a biocompatible glass to a metal substrate. In the preferred embodiment, the process comprises: grit blasting a metallic substrate (e.g., titanium) to remove a surface layer of the metal; after blasting, cleaning the abrasion residue off the surface layer; blending a solvent to use as a suspension agent; creating a suspension of glass-coating powders in the solvent solution; depositing the suspension onto the metallic substrate; drying thoroughly the suspension-coated metallic substrate; inserting the dried, coated substrate into a non-reactive chamber, purging the chamber with an inert gas, such as pure argon; and firing the metallic substrate, inside the furnace, in the inert gas. This process forms a robust fusion between the biocompatible glass/ceramic and titanium, according to preliminary test results. This process can be used for various medical and dental devices, including implants and onplants.
    Type: Application
    Filed: March 6, 2014
    Publication date: September 11, 2014
    Applicant: Covalent Coating Technologies, LLC
    Inventors: Orville G. Bailey, Gary Fischman, Petre Bajenaru
  • Patent number: 8785942
    Abstract: A nitride semiconductor substrate suitable for a normally-off type high breakdown-voltage device and a method of manufacturing the substrate are provided allowing both a higher threshold voltage and improvement in current collapse. In a nitride semiconductor substrate 10 having a substrate 1, a buffer layer 2 formed on one principal plane of the substrate 1, an intermediate layer 3 formed on the buffer layer 2, an electron transport layer 4 formed on the intermediate layer 3, and an electron supply layer 5 formed on the electron transport layer 4, the intermediate layer 3 has a thickness of 200 nm to 1500 nm and a carbon concentration of 5×1016 atoms/cm3 to 1×1018 atoms/cm3 and is of AlxGa1-xN (0.05?x?0.24), and the electron transport layer 4 has a thickness of 5 nm to 200 nm and is of AlyGa1-yN (0?y?0.04).
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: July 22, 2014
    Assignee: Covalent Materials Corporation
    Inventors: Akira Yoshida, Jun Komiyama, Yoshihisa Abe, Hiroshi Oishi, Kenichi Eriguchi, Shunichi Suzuki
  • Publication number: 20140112861
    Abstract: A heat-insulating material is provided in which thermal conductivity is controlled not to increase and good insulation properties are held even in a high temperature range. The heat-insulating material is formed of a spinel porous sintered body having a porosity of 65 to 90 vol. % and represented by a chemical formula XAl2O4 (X?Zn, Fe, Mg, Ni, or Mn) which is arranged such that large pores having a diameter of greater than 1000 ?m occupy 25 vol. % or less of the total pore volume, fine pores having a diameter of 0.45 ?m or less occupy 5 to 40 vol. % of the volume of the pores having a diameter of 1000 ?m or less, at least one pore-diameter distribution peak is within a range of 0.14 to 10 ?m, and is formed of sintered particles having a calculated average particle diameter of 0.04 to 1 ?m.
    Type: Application
    Filed: August 21, 2013
    Publication date: April 24, 2014
    Applicant: Covalent Materials Corporation
    Inventors: Shuko AKAMINE, Mitsuhiro Fujita
  • Patent number: 8691367
    Abstract: A micro channel structure body 10 in which a micro channel 3 having a predetermined cross-sectional shape is formed in a laminate where substrates 1a, 1b, and 1c having formed thereon electrodes 2a, 2b, and 2c made of a thin film are laminated sequentially. The above-mentioned micro channel 3 is formed in a perpendicular direction ? perpendicular to a lamination direction ? of the above-mentioned laminate. Inner surfaces 3a and 3b of the above-mentioned micro channel 3 have an acute angle ? with respect to the lamination direction ? of the above-mentioned laminate. The above-mentioned plurality of electrodes 2a, 2b, and 2c are formed and exposed in the lamination direction ? of the inner surfaces 3a and 3b of the above-mentioned micro channel 3.
    Type: Grant
    Filed: July 16, 2008
    Date of Patent: April 8, 2014
    Assignee: Covalent Materials Corporation
    Inventors: Hiroyuki Goto, Haruo Murayama, Susumu Kimijima, Masahiko Ichishima
  • Patent number: 8673638
    Abstract: The present invention relates to a cell culture support for culturing mesenchymal stem cells, which includes en upper surface including a plurality of wells, in which the upper surface has a root mean square roughness Rq of 100 to 280 nm and a linear density of 1.6 to 10 per 1 ?m length.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: March 18, 2014
    Assignee: Covalent Materials Corporation
    Inventors: Fumihiko Kitagawa, Takafumi Imaizumi, Shunsuke Takei, Itsuki Yamamoto, Yasuhiko Tabata
  • Publication number: 20140055783
    Abstract: A method of analyzing a nitride semiconductor layer in which a mixing ratio at a ternary mixed-crystal nitride semiconductor layer can be analyzed non-destructively, simply, and precisely, even its surface is covered with a cap layer is provided. The nitride semiconductor layer having an AN layer or a BN layer with a thickness of 0.5 to 10 nm that is stacked on an AxB1-xN layer (A and B: 13 group elements, 0?x?1) is subjected to reflection spectroscopy to obtain a reflection spectrum of the AxB1-xN layer. Let an energy value in a peak position of the reflection spectrum be a band gap energy Egap, and let a band gap energy value of AxB1-xN (x=1) be EA and a band gap energy value of AxB1-xN (x=0) be EB, x is calculated from Equation Egap=(1?x)EB+xEA?bx(1?x) (where b is bowing parameter corresponding to A and B).
    Type: Application
    Filed: August 26, 2013
    Publication date: February 27, 2014
    Applicant: Covalent Materials Corporation
    Inventors: Yoshihata YANASE, Hiroshi Shirai, Jun Komiyama, Hiroshi Oishi
  • Patent number: 8637960
    Abstract: A nitride semiconductor substrate is provided in which leak current reduction and improvement in current collapse are effectively attained when using Si single crystal as a base substrate. The nitride semiconductor substrate is such that an active layer of a nitride semiconductor is formed on one principal plane of a Si single crystal substrate through a plurality of buffer layers made of a nitride, in the buffer layers, a carbon concentration of a layer which is in contact with at least the active layer is from 1×1018 to 1×1020 atoms/cm3, a ratio of a screw dislocation density to the total dislocation density is from 0.15 to 0.3 in an interface region between the buffer layer and the active layer, and the total dislocation density in the interface region is 15×109 cm?2 or less.
    Type: Grant
    Filed: October 2, 2012
    Date of Patent: January 28, 2014
    Assignee: Covalent Material Corporation
    Inventors: Yoshihisa Abe, Jun Komiyama, Hiroshi Oishi, Akira Yoshida, Kenichi Eriguchi, Shunichi Suzuki
  • Publication number: 20130315761
    Abstract: The invention relates to a vacuum generator module comprising a substantially rectangular box housing: the pneumatic vacuum generator means and their channels for connection to an admission orifice for admitting a gas under pressure, to a gas exhaust orifice, and to a suction orifice, each orifice opening to the outside via one of the faces of the box; and electronic means for controlling and monitoring the operation of the pneumatic means and their electrical connections with an electrical power supply and external control members using a defined program, including two connectors, one being an input connector, and the other being an output connector likewise installed in one of the faces of the box; the set being characterized in that: the electronic means comprise a multi-network I/O microcontroller suitable for imparting a master or slave function to the module depending on whether the module is or is not directly connected to a fieldbus present in a vacuum handling machine incorporating the module.
    Type: Application
    Filed: February 29, 2012
    Publication date: November 28, 2013
    Applicant: COVAL
    Inventors: Pierre Milhau, Michel Cecchin
  • Publication number: 20130224479
    Abstract: A carbon-fiber-reinforced silicon-carbide-based composite material which has better strength and toughness, and a braking material, such as a brake disc using the composite material, are provided. By using the carbon-fiber-reinforced silicon-carbide-based composite material including a bundle of fibers having chopped carbon fibers arranged in parallel and the other carbon component, carbon, silicon, and silicon carbide, in which the fiber bundle is flat, its cross-section perpendicular to its longitudinal direction has a larger diameter of 1 mm or more, a ratio of the larger diameter to a smaller diameter is from 1.5 to 5, and a plurality of the fiber bundles are randomly oriented substantially along a two-dimensional plane, and a two-dimensional side serves as a braking side to thereby constitute the braking material.
    Type: Application
    Filed: February 21, 2013
    Publication date: August 29, 2013
    Applicant: Covalent Materials Corporation
    Inventor: Covalent Materials Corporation
  • Publication number: 20130082355
    Abstract: A nitride semiconductor substrate is provided in which leak current reduction and improvement in current collapse are effectively attained when using Si single crystal as a base substrate. The nitride semiconductor substrate is such that an active layer of a nitride semiconductor is formed on one principal plane of a Si single crystal substrate through a plurality of buffer layers made of a nitride, in the buffer layers, a carbon concentration of a layer which is in contact with at least the active layer is from 1×1018 to 1×1020 atoms/cm3, a ratio of a screw dislocation density to the total dislocation density is from 0.15 to 0.3 in an interface region between the buffer layer and the active layer, and the total dislocation density in the interface region is 15×109 cm?2 or less.
    Type: Application
    Filed: October 2, 2012
    Publication date: April 4, 2013
    Applicant: Covalent Materials Corporation
    Inventor: Covalent Materials Corporation
  • Publication number: 20130084450
    Abstract: The present invention relates to a corrosion resistant member including: a substrate composed of a ceramic or a metal, and at least one layer of a corrosion resistant film formed on a surface of at least a region of the substrate to be exposed to plasma or a corrosive gas, in which the corrosion resistant film contains yttria as a main component and further also contains at least one of tantalum and niobium in an amount of 0.02 to 10 mol % in terms of pentoxide relative to the yttria, and a non-melted portion is not present in the corrosion resistant film.
    Type: Application
    Filed: September 7, 2012
    Publication date: April 4, 2013
    Applicant: Covalent Materials Corporation
    Inventors: Yukitaka MURATA, Hitoshi SASAKI, Shintaro MATSUMOTO
  • Publication number: 20130078588
    Abstract: A method for heat-treating a silicon wafer is provided in which in-plane uniformity in BMD density along a diameter of a bulk of the wafer grown by the CZ process can be improved. Further, a method for heat-treating a silicon wafer is provided in which in-plane uniformity in BMD size can also be improved and COP of a surface layer of the wafer can be reduced. The method includes a step of a first heat treatment in which the CZ silicon wafer is heated to a temperature from 1325 to 1400° C. in an oxidizing gas atmosphere, held at the temperature, and then cooled at a cooling rate of from 50 to 250° C./second, and a step of a second heat treatment in which the wafer is heated to a temperature from 900 to 1200° C. in a non-oxidizing gas atmosphere, held at the temperature, and then cooled.
    Type: Application
    Filed: September 25, 2012
    Publication date: March 28, 2013
    Applicant: Covalent Silicon Corporation
    Inventors: Takeshi Senda, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Susumu Maeda
  • Patent number: 8399341
    Abstract: The invention is to provide a method for heat treating a silicon wafer reducing grown-in defects while suppressing generation of slip during RTP and improving surface roughness of the wafer. The method performing a first heat treatment while introducing a rare gas, the first heat treatment comprising the steps of rapidly heating the wafer to T1 of 1300° C. or higher and the melting point of silicon or lower, keeping the wafer at T1, rapidly cooling the wafer to T2 of 400-800° C. and keeping the wafer at T2; and performing a second heat treatment while introducing an oxygen gas in an amount of 20-100 vol. %, the second heat treatment comprising the steps of keeping the wafer at T2, rapidly heating the wafer from T2 to T3 of 1250° C. or higher and the melting point of silicon or lower, keeping the wafer at T3 and rapidly cooling the wafer.
    Type: Grant
    Filed: May 17, 2010
    Date of Patent: March 19, 2013
    Assignee: Covalent Materials Corporation
    Inventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Kumiko Murayama, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima
  • Publication number: 20120241912
    Abstract: There is provided a thermal treatment method of a silicon wafer. The method includes the successive steps of: (a) terminating silicon atoms existing on an active surface of the silicon wafer with hydrogen, wherein the active surface is mirror-polished, and a semiconductor device is to be formed on the active surface; (b) terminating the silicon atoms existing on the active surface of the silicon wafer with fluorine; (c) rapidly heating the silicon wafer to a first temperature under an inert gas atmosphere or a reducing gas atmosphere, wherein the first temperature is in a range of 1300° C. to 1400° C.; (d) holding the silicon wafer at the first temperature for a certain time; and (e) rapidly cooling the silicon wafer.
    Type: Application
    Filed: March 15, 2012
    Publication date: September 27, 2012
    Applicant: Covalent Materials Corporation
    Inventors: Takeshi SENDA, Koji Araki
  • Patent number: 8252700
    Abstract: In a method of heat treating a wafer obtained by slicing a silicon single crystal ingot manufactured by the Czochralski method, a rapid heating/cooling heat treatment is carried out by setting a holding time at an ultimate temperature of 1200° C. or more and a melting point of silicon or less to be equal to or longer than one second and to be equal to or shorter than 60 seconds in a mixed gas atmosphere containing oxygen having an oxygen partial pressure of 1.0% or more and 20% or less and argon, and an oxide film having a thickness of 9.1 nm or less or 24.3 nm or more is thus formed on a surface of the silicon wafer.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: August 28, 2012
    Assignee: Covalent Materials Corporation
    Inventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Kumiko Murayama, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima
  • Publication number: 20120184091
    Abstract: The invention is to provide a method for heat treating a silicon wafer reducing grown-in defects while suppressing generation of slip during RTP and improving surface roughness of the wafer. The method performing a first heat treatment while introducing a rare gas, the first heat treatment comprising the steps of rapidly heating the wafer to T1 of 1300° C. or higher and the melting point of silicon or lower, keeping the wafer at T1, rapidly cooling the wafer to T2 of 400-800° C. and keeping the wafer at T2; and performing a second heat treatment while introducing an oxygen gas in an amount of 20-100 vol. %, the second heat treatment comprising the steps of keeping the wafer at T2, rapidly heating the wafer from T2 to T3 of 1250° C. or higher and the melting point of silicon or lower, keeping the wafer at T3 and rapidly cooling the wafer.
    Type: Application
    Filed: May 17, 2010
    Publication date: July 19, 2012
    Applicant: Covalent Materials Corporation
    Inventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Kumiko Murayama, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima
  • Patent number: 8216921
    Abstract: A method for producing a silicon wafer for epitaxial substrate which includes a first step of performing thermal oxidization on a silicon wafer containing boron atoms no less than 1E19 atoms/cm3, thereby forming a silicon oxide film on the surface of the silicon wafer, a second step of peeling off the silicon oxide film, and a third step of performing heat treatment on the silicon wafer in a hydrogen atmosphere.
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: July 10, 2012
    Assignee: Covalent Materials Corporation
    Inventor: Tatsuo Fujii