Abstract: A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.

Abstract: An error message handling buffer comprises a first buffer and a second buffer. A first index is associated with the first buffer and a second index is associated with the second buffer. A buffer controller is operable to write and read messages in the buffer, such that messages are written to the buffer of the first and second buffers that has a buffer index value lesser than the buffer size, and read from the other of the first and second buffers, the other buffer having an index value greater than or equal to the buffer size.

Abstract: Systems and methods provide a display indicating performance characteristics of a computer application. The display may include a call graph having nodes that represent subunits of the application. A first set of statistics for the subunit may be represented in the size or dimensions of the node. A second set of statistics may be displayed in the interior of the node. A third set of statistics may be displayed in response to selecting the node.

Abstract: Control messages are sent from a control processor to a plurality of attached processors via a control tree structure comprising the plurality of attached processors and branching from the control processor, such that two or more of the plurality of attached processor nodes are operable to send messages to other attached processor nodes in parallel.

Abstract: A method and apparatus to provide specifiable ordering between and among vector and scalar operations within a single streaming processor (SSP) via a local synchronization (Lsync) instruction that operates within a relaxed memory consistency model. Various aspects of that relaxed memory consistency model are described. Further, a combined memory synchronization and barrier synchronization (Msync) for a multistreaming processor (MSP) system is described. Also, a global synchronization (Gsync) instruction provides synchronization even outside a single MSP system is described. Advantageously, the pipeline or queue of pending memory requests does not need to be drained before the synchronization operation, nor is it required to refrain from determining addresses for and inserting subsequent memory accesses into the pipeline.

Abstract: A system and method for allocating system resources is described herein. In one embodiment, the method comprises creating, in a computer system, a resource consumer and assigning the resource consumer one of a set of flavors. The method further includes determining whether the resource consumer is limited to receiving resources from a certain one of a set of resource providers, wherein each of the set of resource providers has one of the set of flavors. The method further includes marking a field to indicate that the resource consumer is limited to receiving resources from the certain one of the set of resource providers, if the resource consumer is limited to receiving resources from the certain one of the set of resource providers. The method further includes allocating a resource to the resource consumer from one of the set of resource providers whose flavor matches the flavor assigned to the resource consumer.

Abstract: A computerized system comprising multiple processing nodes, a physical channel configured to transfer data between a memory local to a processing node and a network target remote from the processing node, and a block transfer engine configured to allocate multiple virtual channels to the physical channel and to transfer multiple address-overlapping blocks of data simultaneously using the virtual channels.

Abstract: Systems and methods provide a display indicating performance characteristics of a computer application. The display may include a call graph having nodes that represent subunits of the application. A first set of statistics for the subunit may be represented in the size or dimensions of the node. A second set of statistics may be displayed in the interior of the node. A third set of statistics may be displayed in response to selecting the node.

Abstract: A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.

Abstract: A multiprocessor computer system comprises one or more watchdog timers operable to detect failure of a memory operation based on passage of a certain timing period from a memory operation being issued without a valid response. An error handler is operable to take corrective action regarding the failed memory operation, such as to provide at least one of hardware state management and application state management.

Abstract: A processor core, comprises one or more vector units operable to change between a fine-grained vector mode having a shorter maximum vector length and a coarse-grained vector mode having a longer maximum vector length. Changing vector modes comprises halting all instruction stream execution in the core, flushing one or more registers in a register space, reconfiguring one or more vector registers in the register space, and restarting instruction execution in the core.

Abstract: Various embodiments include fault tolerant memory apparatus, methods, and systems, including an apparatus comprising a memory device including a plurality of addressable memory locations, and a memory manager coupled to the memory device, the memory manager including a scheduling unit operable to detect a multi-bit error in data read from the memory device, and to retry the read operation in order to distinguish between an intermittent error and a persistent error.

Abstract: In some embodiments, the present invention relates to a method of maintaining a global clock within a multiprocessor system having a plurality of nodes that are connected in a network via links. A virtual spanning tree is mapped onto the network and the nodes and the links are configured such that each node is in a parent-child relationship with one or more other nodes in the virtual spanning tree. A global clock is generated in a root of the virtual spanning tree and global clock signals are communicated down the virtual spanning tree to each of the nodes.

Abstract: A multiprocessor computer system comprises a plurality of nodes, wherein the nodes are ordered using a snaking dimension-ordered numbering. An application placement module is operable to place an application in nodes with preference given to nodes ordered near one another.

Abstract: One embodiment includes an integrated circuit including an input circuit, a first diode including a first anode and a first cathode, with the first cathode coupled to a first voltage, the first anode coupled to the input circuit at a node via a first mechanical switch, a second diode including a second anode and a second cathode, with the second cathode coupled to the node via a second mechanical switch, the second anode coupled to a ground and a resistor coupled to the input circuit between the integrated circuit and the node, wherein in a first mode of operating, the first mechanical switch and the second mechanical switch are conducting, and in a second mode of operating, the first and second mechanical switches are nonconducting.

Abstract: A multiprocessor computer system comprises a dragonfly processor interconnect network that comprises a plurality of processor nodes and a plurality of routers. The routers are operable to route data by selecting from among a plurality of network paths from a target node to a destination node in the dragonfly network based on one or more routing tables.

Abstract: A multiprocessor computer system comprises a dragonfly processor interconnect network that comprises a plurality of processor nodes and a plurality of routers. The routers are operable to adaptively route data by selecting from among a plurality of network paths from a target node to a destination node in the dragonfly network based on one or more of network congestion information from neighboring routers and failed network link information from neighboring routers.

Abstract: A high-radix interprocessor communications system and method having a plurality of processor nodes, a plurality of first routers and a plurality of second routers. Each first router is connected to a processor node and to two or more second routers. Each first router includes input ports, output ports, row busses, columns channels and a plurality of subswitches arranged in a n x p matrix. Each row bus receives data from one of the plurality of input ports and distributes the data to two or more of the plurality of subswitches. Each column distributes data from one or more subswitches to one or more output ports. Each row bus includes a route selector, wherein the route selector includes a routing table which selects an output port for each packet and which routes the packet through one of the row busses to the selected output port.

Abstract: Computer systems and associated methods for cooling computer components are disclosed herein. One embodiment of a computer system includes a computer cabinet having an air inlet spaced apart from an air outlet. The computer system also includes heat exchangers positioned in the computer cabinet, and a heat removal system in fluid communication with the heat exchangers. The computer system additionally includes at least one sensor for monitoring heat transfer between the computer cabinet and the room. The computer system further includes a control system operatively coupled to the at least one sensor, the control system including a computer-readable medium holding instructions for determining whether heat transfer between the computer cabinet and the room is balanced based on information from the sensor, and if not, adjusting a parameter to balance the heat transfer.

Abstract: A processor is operable to execute a bit matrix multiply instruction. In further examples, the processor is operable to perform a vector bit matrix multiply instruction, and is a part of a computerized system.