Abstract: A test access port controller for use in a level sensitive scan design having test design logic including at least one serial scan test path. The test access port controller includes test access port controller logic operable in a system test mode for controlling the serial shifting of input test data into the at least one serial scan test path and for controlling serial shifting of resulting output test data out of the at least one serial scan test path after performance of system mode test under control of a test clock. The test access port controller further includes clock logic for providing the test clock to the test access port controller logic and the test design logic in system test mode.

Abstract: Division system and method support a hardware division address centrifuge to provide a flexible addressing scheme, and thus facilitates the reorganization and redistribution of data between remote and local memory blocks in a distributed memory massively parallel processing system. A flexible addressing scheme supports data organizations which can vary widely, depending on the processing task. Different data organizations in memory are supported by a PE internal address having certain bits designated as the target PE number and the remaining bits designating the offset within that PE's local memory. The PE and offset bits are distributed throughout the PE internal address to achieve various data distributions throughout memory. When a transfer occurs, the PE number bits and offset bits are separated via the centrifuge under control of a software-supplied mask.

Abstract: A method for extracting a PE number and offset from an array index by recursive centrifuging. According to one aspect of the present invention, a processing element number is assigned to each processing element, a local memory address is assigned to each memory location and a linearized index is assigned to each array element in a multidimensional array. The processing element number of the processing element in which a particular array element is stored is computed as a function of a linearized index associated with the array element and a mask word determined from the distribution specification associated with the array. The mask word is generated from the distribution specification and applied to a linearized index associated with a particular array element to obtain processing element number bits and local offset bits.

Abstract: An information handling system includes stacks of printed circuit boards interconnected using an interconnection system. The printed circuit boards include network boards, system interface boards, memory boards, and central processing unit boards. The interconnection system for electrically connecting the various printed circuit boards includes a set of interconnection modules placed adjacent one another to form a substantially aligned row. The interconnection modules can be used to connect one stack to an orthogonally oriented stack or to a parallel oriented stack. The printed circuit board used in the interconnection system includes an inner rail positioned near the edge of the printed circuit board, an outer rail positioned near the edge of the printed circuit board, and an alignment stop attached to or positioned near one of the inner or outer rail. The most distant interconnection module of a row of aligned modules includes a spring attached thereto.

Abstract: A multiprocessor computer system includes processing element nodes interconnected by physical communication links. Routers route messages between processing element nodes on the physical communication links. Each router includes input ports for receiving messages, output ports for sending messages from the router, two types of virtual channels, a lookup table associated with the input port having a lookup table virtual channel number, and a virtual channel assignment mechanism. The virtual channel assignment mechanism assigns an output next virtual channel number for determining the type of virtual channel to be used for routing from a next router along a given route. The next virtual channel number is assigned based on the lookup table virtual channel number and an input next virtual channel number received from a previous router along the given route.

Abstract: Vector shifting elements of a vector register by varying amounts in a single process is achieved in a vector supercomputer processor. A first vector register contains a set of operands, and a second vector register contains a set of shift counts, one shift count for each operand. Operands and shift counts are successively transferred to a vector shift functional unit, which shifts the operand by an amount equal to the value of the shift count. The shifted operands are stored in a third vector register. The vector shift functional unit also achieves word shifting of a predetermined number of vector register elements to different word locations of another vector register.

Abstract: An input cell to the core logic on an electrical component and an output cell from the core logic on an electrical component are provided with a first signal path for data, a second signal path for scan data, a flip flop positioned near the pad of the core logic for selecting between said first signal path for data and second signal path for scan data. The scan data is used to input special signals or vectors to the core logic and to read the results of the scan data after it has passed through the core data and has been manipulated thereby. Several of the electrical components can be electrically connected to one another. The output cell of a first chip is electrically attached to the input cell of a second electrical component.

Abstract: Improved method and apparatus for facilitating barrier and eureka synchronization in a massively parallel processing system. The present barrier/eureka synchronization mechanism provides a partitionable, low-latency, immediately reusable, robust mechanism which can operate on a physical data-communications network and can be used to alert all processor entities (PEs) in a partition when all of the PEs in that partition have reached a designated barrier point in their individual program code, or when any one of the PEs in that partition has reached a designated eureka point in its individual program code, or when either the barrier or eureka requirements have been satisfied, which ever comes first. Multiple overlapping synchronization partitions are available simultaneously through the use of a plurality of parallel synchronization contexts.

Abstract: A multiprocessor computer system includes processing element nodes interconnected with physical communication links in an n-dimensional topology. A flow controlled virtual channel has virtual channel buffers assigned to each physical communication link to store packets containing information to be transferred between the processing element nodes. A non-flow controlled virtual maintenance channel has maintenance channel buffers assigned to each physical communication link to store packets of maintenance information to be transferred between the processing element nodes. The virtual maintenance channel is assigned a higher priority for accessing the physical communication links than the flow controlled virtual channel.

Abstract: The invention is a computer module for scalably adding computing power and cooling capacity to a computer system. Computing power can be added by merely adding additional printed circuit cards to the computing module. Cooling capability is added by adding heat pipes to the computer module. The computing module for a computer includes a first heat pipe assembly. The first heat pipe assembly has an evaporator plate with an evaporator surface. The first heat pipe also has a condenser in fluid communication with the evaporator plate. The evaporator plate is positioned adjacent one side of a printed circuit board populated with at least one electronic component. The computing module may use a printed circuit board which has two sides populated with electronic components.

Abstract: A system and method of accessing a memory location within a system having a processor and a plurality of memory locations separate from the processor. The system includes a plurality of external registers which are connected to the processor over a data bus, address translation means, connected to the processor over the data bus and an address bus, for calculating, based on an index written to the data bus, an address associated with one of the memory locations, and transfer means, connected to the plurality of external registers, for transferring data between the addressed memory location and one of the external registers.

Abstract: A heat sink is disclosed having an elongate, porous metal structure, including multiple sets of thermally conductive members. The members, which are interwoven, direct heat away from a heat producing component. The elongate structure of the matrix structure can be formed in a variety of predetermined forms, including a coiled structure or an elliptically coiled structure. Alternatively, the matrix structure is plated for added thermal conductivity between the sets of members. In addition, air flow is directed over the heat sink for added convection of heat. The heat sink is fabricated using a mesh of thermally conductive material such as copper or aluminum and can be provided with a plurality of protuberances. The heat sink is thermally bonded to the heat producing component. Alternatively, the heat sink has a ledge for sealing with a duct.A method for cooling a heat producing component is also disclosed.

Abstract: Method and apparatus for a logical address translator which translates a logical address into a physical address in a computer. The computer includes a plurality of address ports. Each address port includes a logical address translator, which includes a plurality of segment-register sets. Each segment-register set holds values which specify address boundaries and translation mapping of a corresponding logical segment. A segment detector is coupled to the plurality of segment-register sets, wherein the segment detector operates to determine whether the logical address is within the specified address boundaries of the logical segment. An address mapper is coupled to the plurality of segment-register sets, wherein the address mapper operates to translate the logical address into a physical address.

Abstract: The precise detection of errors in computer programs using the hardware watchpoint mechanism found in computers is disclosed. In one embodiment, a software detection phase of a method detects the approximate location of an error, generating information regarding this approximate location. In this embodiment, a hardware watchpoint phase of the method detects the precise location of the error based on the information generated by the software detection phase, generating information regarding the precise location. Finally, in this embodiment of the invention, a debugger phase of the method identifies the statement in the computer program causing the error, based on the information generated by the hardware watchpoint phase.

Abstract: A multiprocessor computer system includes processing element nodes interconnected by physical communication links in a n-dimensional topology, which includes at least two global partitions. Routers route messages between processing element nodes and include ports for receiving and sending messages, and lookup tables having a local router table having directions for routing between processor element nodes within a global partition, and a global router table having directions for routing between processor element nodes located in different global partitions.

Abstract: The present invention discloses a method and apparatus for bridging the gap between an integrated circuit package or component mounted on a circuit board and a heat sink such that there is little stress placed on the component, but there is still a connection between the component and the heat sink for dissipation of heat. The invention provides mechanical integrity for delicate component packages, and in doing so allows for the use of a variety of heat sinks to provide cooling. A printed circuit board has integrated circuit packages or other components mounted to the circuit board. A cooling cap comprised of a thermally conductive material is mounted on the circuit board, such that the component is enveloped by the circuit board and cooling cap. A layer of thermally conductive material may be deposited between the component and the cooling cap to provide a thermally conductive path from the component to the cooling cap.

Abstract: Method and apparatus for watermarking digital video material by embedding a digital signature. One embodiment of the system integrates the embedding procedure into a block-based compression scheme. In one embodiment, a 32-bit digital signature is embedded into the x- and y-coordinates of motion vectors. Since not all motion vectors are suitable for coding (with regard to objectionable visible artifacts), three hybrid selection criteria have been developed for determining whether or not to code a motion vector. A probabilistic coding procedure has also been developed to avoid problems that arise when fewer than 16 blocks and/or vectors (where 16 vectors correspond to 32 bits) can be coded in a frame. One such procedure makes use of binary random sequences to virtually code the signature into the motion vectors. The system has been implemented on a CRAY T3D massively parallel supercomputer, where a near-real-time (5 frames per second) embedding of the signature is obtainable.

Abstract: A congestion control mechanism for a node of a modular computer network system. The mechanism includes registers for maintaining the number of undelivered requests and unanswered requests for the node and registers for the maximum number of such undelivered requests and unanswered requests. The mechanism regulates congestion on the network by throttling back or ratcheting up the allowed number of undelivered requests and unanswered requests based upon the level of busy and non-busy results of such requests and answers. Congestion is also alleviated by the implementation of a set of large and small send and receive buffers. These buffers are configurably partitioned among virtual I/O channels. Each request virtual I/O channel may utilitize congestion control.

Abstract: A vector/scalar computer system has nodes interconnected by an interconnect network. Each node includes a vector execution unit, a scalar execution unit, physical vector registers holding physical vector elements, a mapping vector register holding a mapping vector, and a memory. The physical vector registers from nodes together form an architectural vector register having architectural vector elements. The mapping vector defines an assignment of architectural vector elements to physical vector elements for its node. The memories from the nodes together form an aggregate memory.

Abstract: A vector processing system which uses vector masks to determine whether or not to perform operations on operands corresponding to bit positions within the mask is disclosed. An approximation of the number of no-operation representative bits in a vector mask register is made, and such bits are skipped to improve the performance of vector mask based operations. The number of consecutive no-op representative bits, as represented by zero values, skipped is a power of two to simplify the circuitry and logic involved in skipping such operations.