Abstract: A sequence of conditional vector IF statements is processed by employing a mask register and a condition register. Each conditional vector IF statement is typically performed on two vector registers, each having vector elements. A first conditional vector IF statement in the sequence is processed for those vector elements corresponding to set bits in the mask register. Bits are set in the condition register to reflect those vector elements which correspond to the set bits in the mask register for which the conditional vector IF statement is satisfied. The contents of the condition register are then moved into the mask register. A next conditional vector IF statement in the sequence is then processed for those vector elements corresponding to the new set bits in the mask register. Bits are then set in the condition register to reflect those vector elements which correspond to the new set bits in the mask register for which the conditional vector IF statement is satisfied.

Abstract: A processor to memory interconnect network can be used to construct both small and large scale multiprocessing systems. The interconnect network includes network modules and memory modules. The network and memory modules are constructed of a series of n.times.m switches, each of which route n inputs to m outputs. The switches are designed such that message contention in the interconnect network is reduced. The switches, and thus the memory and network modules are highly modular, thus allowing virtually any scale multiprocessing system to be constructed utilizing the same components.

Abstract: Method and apparatus for vector processing on a computer system. As the last element of a group of elements (called a "chunk") in a vector register is loaded from memory, the entire chunk is marked valid and thus made available for use by subsequent or pending operations. The vector processing apparatus comprises a plurality of vector registers, wherein each vector register holds a plurality of elements. For each of the vector registers, a validity indicator is provided wherein each validity indicator indicates a subset of the elements in the corresponding vector register which are valid. A chunk-validation controller is coupled to the validity indicators operable to adjust a value of the validity indicator in response to a plurality of elements becoming valid. An arithmetic logical functional unit (ALFU) is coupled to the vector registers to execute functions specified by program instructions.

Abstract: A vector processor includes functional unit paths, each having an input and an output, and with at least one functional unit path including a plurality of pipelined functional elements coupled to the respective path input and output in parallel. The functional elements have different pipeline lengths to complete processing of operands applied to the path input. Program instruction initiation means responds to a first instruction to initiate processing of first operand data in a first of the functional elements, and responds to a second instruction to initiate the processing of second operand data in a second of the functional elements dependent upon completion of the first instruction but only if the second functional element has a pipeline length equal to or greater than the pipeline length of the first functional element.

Abstract: A communications protocol having a plurality of signals, wherein the plurality of signals includes data packets, control packets, checksum packets and sync symbols. One of the control packets is transmitted after a sync symbol is transmitted. One of the sync symbols, data packets or checksum packets is transmitted after the control packet is transmitted. One of the sync symbols is transmitted after one of said checksum packets is transmitted and one of the sync symbols or another of the data packets is transmitted after one of the data packets is transmitted.

Abstract: A method of setting array boundaries in order to simplify addressing across processor elements in a distributed memory system having global addressing. Each dimension of an array is examined to determine a lower bound, a declared upper bound and an implicit upper bound. The lower bound and the declared upper bound in each dimension are used to set limits for operations on array elements while the implicit upper bound calculated from the lower bound and the declared upper bound is used in calculating the location (processor element and offset) of a particular array element.

Abstract: A multidimensional interconnection and routing apparatus for a parallel processing computer connects together processing elements in a three-dimensional structure. The interconnection and routing apparatus includes a plurality of processing element nodes. A communication connects at least one of the processing elements with a host system. An interconnection network connects together the processing element nodes in an X, Y, and Z dimension. The network includes communication paths connecting each of the plurality of processing elements to adjacent processing elements in the plus and minus directions of each of the X, Y, and Z dimensions.

Abstract: A messaging facility is described that enables the passing of packets of data from one processing element to another in a globally addressable, distributed memory multiprocessor without having an explicit destination address in the target processing element's memory. The messaging facility can be used to accomplish a remote action by defining an opcode convention that permits one processor to send a message containing opcode, address and arguments to another. The destination processor, upon receiving the message after the arrival interrupt, can decode the opcode and perform the indicated action using the argument address and data. The messaging facility provides the primitives for the construction of an interprocessor communication protocol. Operating system communication and message-passing programming models can be accomplished using the messaging facility.

Abstract: A method of managing distributed memory in which a local memory is partitioned into a shared heap segment, a shared stack segment, a private heap segment and a private stack segment. One of the segments starts at a fixed address and grows upward. A second segment starts at a fixed address and grows downward. A third segment starts at a relocatable segment wall and grows downward and a fourth segment starts at a relocatable segment wall and grows upward.

Abstract: A method of accessing common memory in a cluster architecture for a highly parallel multiprocessor scaler/factor computer system using a plurality of segment registers in which is first determined whether a logical address is within a start and end range as defined by the segment registers and then relocating the logical address to a physical address using a displacement value in another segment register.

Abstract: The present invention includes a tooling apparatus designed to provide accurately aligned printed circuits on both major sides of a printed circuit board layer, especially advantageous for use in multi-layer PCB's. Also disclosed is the method manufacture of the apparatus and the methods of using the apparatus. The apparatus includes patterns formed on glass masks attached to frames incorporating alignment pins and slots. The patterns include registration marks for alignment during manufacture of the apparatus. During use, the apparatus allows accurate alignment of patterns on both sides of a PCB layer. Also disclosed is the apparatus with buttons used to pattern PCB layers having pre-drilled Z-axis holes.

Abstract: The present invention is an improved high performance scalar/vector processor. In the preferred embodiment, the scalar/vector processor is used in a multiprocessor system. The scalar/vector processor is comprised of a scalar processor for operating on scalar and logical instructions, including a plurality of independent functional units operably connected to the scalar processor, a vector processor for operating on vector instructions, including a plurality of independent functional units operably connected to the vector processor, and an instruction control mechanism for fetching both the scalar and vector instructions from an instruction cache and controlling the operation of those instructions in both the scalar and vector processor. The instruction control mechanism is designed to enhance the performance of the scalar/vector processor by keeping a multiplicity of pipelines substantially filled with a minimum number of gaps.

Abstract: A clock distribution system minimizes clock skew in the distribution of clock signals to individual circuit board components in a highly synchronous, high speed computer system. The clock system includes an optical subsystem and an electrical subsystem. The optical subsystem utilizes multiple lasers and an n.times.n passive star coupler to introduce clock redundancy into the system. The lengths of the optical distribution fibers are controlled such that they are of equivalent optical path length. Once delivered to the logic assemblies, the optical clock signals are converted into equivalent electrical clock signals. The electrical subsystem then distributes the converted electrical clock signals to individual circuit board components over equalized fanout paths such that the skew as seen by the individual components is minimized. The system also compensates for skew introduced by the receiver and fanout electronics by tuning the length of the fiber.

Abstract: A method of synchronizing accesses to shared data in a multiprocessing system having an atomic swap capability. A distinguished lock value is defined. A processor which wishes to access a shared data memory location performs an atomic swap of the lock value to the shared data memory location. If the data received from the atomic swap is equivalent to the lock value the processor knows that the memory location has been locked by another processor. The processor then repeats the atomic swap at intervals until data is received which is not equivalent to the lock value. The processor operates on the data and then performs a write to the shared data memory location to replace the lock value with the updated data. In an alternate embodiment, in situations where a unique lock value cannot be defined, an array is created to store lock values associated with particular shared data memory locations.

Abstract: A method of routing messages within an n-dimensional network topology. Two directions are associated with each dimension in the n-dimensional network, for a total of 2n directions. A direction order is assigned which prioritizes the order in which a packet is routed across the 2n possible directions. Such an approach provides deadlock-free, fault tolerant wormhole routing in networks without wrap-around channels. For networks with wrap-around channels, the above method of wormhole routing is enhanced by placing a first direction from each of the n dimensions within a first group of directions. The second direction from each dimension is placed within a second group of directions. A packet to be routed from a source node to a destination node is routed in all relevant directions in the first group of directions in any order before being routed in the second group of directions.

Abstract: A system for interprocessor communication including a shared register resource accessible by any one of the processors through the using internal communication paths. The shared register resource is distributed among the processors with each processor including a portion of the total system resource. Each processor includes an access circuit for receiving instructions from the CPU and generating control bytes to be distributed to the shared register resource circuits in each of the processors, which use the control byte to control shared resource access. Each shared register resource circuit is capable of controlling the I/O channels associated with its respective processor. A local access circuit for each CPU is capable of obtaining access to and controlling any of the I/O channels in the system via the shared register resource circuits.

Abstract: A global register system provides communication and coordination among a plurality of processors sharing a common memory in a multiprocessor system which access one or more registers within a shared resource circuit that is separate from the common memory and is symmetrically accessible by the plurality of processors in the multiprocessor system. The global register system is accessed by direct addresses determined by the processor from a previously assigned indirect address and an instruction accessing the data stored in global registers. Arithmetic or logic operation on a data value stored in a selected one of the registers are performed by the global register system independent from the processors or the common memory in order to modify the data value in the selected global register as part of an atomic operation performed in response to a single read-and-modify instruction received from one of the processors.

Abstract: A method and apparatus for providing a resource lockout mechanism in a shared memory, multiprocessor system that is capable of performing both a read and write operation during the same memory operation. The load and flag instruction of the present invention can execute a read operation, followed by a write operation of a preselected flag value to the same memory location during the same memory operation. The load and flag instruction is particularly useful as a resource lockout mechanism for use in Monte Carlo applications.

Abstract: An method and apparatus for testing the frequency characteristics of electrical connections between integrated circuits. The apparatus includes circuitry for transmitting a series of signals via the connection from one integrated circuit to another. Each signal of the series is transmitted at a different frequencies. The apparatus further includes circuitry for receiving the series of signals and generating an error signal for each frequency. The method includes sending the series of pre-determined signals from one integrated circuit to another and receiving the series of signals. The method further including the evaluation of the series of signals and the generation of error signals corresponding to each frequency.