Abstract: In a tightly coupled communication scheme based on a common shared resource circuit having a plurality of shared information registers and adapted particularly to a multiprocessing system having 2.sup.N CPUs, a method of performing a read-and-modify instruction. Data stored in a shared information register is read from the shared register, captured in a read and increment circuit and sent to the processor issuing the read-and-modify instruction. At the same time, a mathematical function is performed on the captured data is incremented and the result is written back into the shared information register.

Abstract: A vector/scalar computer system has nodes interconnected by an interconnect network. Each node includes a vector execution unit, a scalar execution unit, physical vector registers, and a memory. The physical vector registers from the nodes together form an architectural vector register, which are references by vector applications. Memories from nodes together form an aggregate memory. The vector applications load memory vector elements from the memories to the physical vector registers, and store physical vector elements from the physical vector registers to the memories. The memory vector elements are interleaved among the memories of the nodes to reduce inter-node traffic during the loads and the stores.

Abstract: An efficient integer-division-by-an-constant method and apparatus. This integer-division-by-an-constant is useful in calculations which must be performed often and/or quickly, and where the denominator is fixed for the calculations, such as address calculations in massively parallel, distributed memory processor systems. Also described is a method and apparatus using the integer-division-by-an-constant method and apparatus, which facilitates removing power-of two restrictions on the reorganization and redistribution of data between remote and local memory blocks in a massively parallel, distributed-memory processing system. The flexible addressing scheme provided supports data organizations which vary widely depending on the processing task. In particular, a plurality of processing elements (PEs) operating in parallel within a subset of all the PEs in a massively parallel processor system, may simultaneously operate on an array data structure, the array data structure having an arbitrary size and shape.

Abstract: A virtual memory management system for a vector based processing system detects early page or segment faults allowing pipelined instructions to be halted and resumed once the pages or segments required for a job are available in main storage. A multiplier is used for stride accesses, and min and max registers are used for gather/scatter instructions to provide a range of addresses to be accessed during a job. These ranges are determined early enough in execution of instructions related to a job to allow saving the state of the processor and resuming execution of the instructions once the data is available in main storage.

Abstract: A system and method of transferring information between a peripheral device and an MPP system having an interconnect network and a plurality of processing nodes. Each processing element includes a processor, local memory and a router circuit connected to the interconnect network, the processor and the local memory. Each router circuit includes means for transferring data between the processor and the interconnect network and means for transferring data between the local memory and the interconnect network. An I/O controller is connected to a plurality of the router circuits. Data is then read from the peripheral device and transferred through the I/O controller to local memory of one of the processing elements.

Abstract: A system and method for implementing a serial RAID system. Data is striped for the array of disk drives and parity for the striped data is calculated and the resulting data and is written serially to a RAID system over a Fibre Channel or other type of network. The system also allows reading of the striped data and parity serially from the disk array.

Abstract: Vector shifting elements of a vector register by varying amounts in a single process is achieved in a vector supercomputer processor. A first vector register contains a set of operands, and a second vector register contains a set of shift counts, one shift count for each operand. Operands and shift counts are successively transferred to a vector shift functional unit, which shifts the operand by an amount equal to the value of the shift count. The shifted operands are stored in a third vector register. The vector shift functional unit also achieves word shifting of a predetermined number of vector register elements to different word locations of another vector register.

Abstract: A messaging facility in a multiprocessor computer system includes assembly circuitry in a source processing element for assembling a message to be sent from the source processing element to a destination processing element based on information provided from a processor in the source processing element. A network router transmits the assembled message from the source processing element to the destination processing element via an interconnect network. A message queue in a local memory of the destination processing element stores the transmitted message. A control word stored in the local memory of the destination processing element includes a limit field designating a size of the message queue and a tail field designating an index into the corresponding message queue to indicate a location in the message queue where the transmitted message is to be stored. Shell circuitry in the destination processing element atomically reads and updates the tail field.

Abstract: A system and method of accessing a memory location within a system having a processor and a plurality of memory locations separate from the processor. The system includes a plurality of external registers which are connected to the processor over a data bus, address translation means, connected to the processor over the data bus and an address bus, for calculating, based on an index written to the data bus, an address associated with one of the memory locations, and transfer means, connected to the plurality of external registers, for transferring data between the addressed memory location and one of the external registers.

Abstract: The present invention discloses a method and apparatus for bridging the gap between an integrated circuit package or component mounted on a circuit board and a heat sink such that there is little stress placed on the component, but there is still a connection between the component and the heat sink for dissipation of heat. The invention provides mechanical integrity for delicate component packages, and in doing so allows for the use of a variety of heat sinks to provide cooling. A printed circuit board has integrated circuit packages or other components mounted to the circuit board. A cooling cap comprised of a thermally conductive material is mounted on the circuit board, such that the component is enveloped by the circuit board and cooling cap. A layer of thermally conductive material may be deposited between the component and the cooling cap to provide a thermally conductive path from the component to the cooling cap.

Abstract: A system for implementing RAID-5 parity generation and reconstruction. Data for an array of disk drives is placed in an I/O buffer. The RAID-5 parity engine creates parity data and stores the resulting parity data in the I/O buffer as well. The I/O buffer (both the data and the parity) is then sector-striped across a network of disk drives, such as a Fibre Channel network. The RAID-5 parity engine creates parity on multiple stripes of data upon a single activation of the engine. The RAID-5 parity engine can reconstruct a sector of data using the parity information. The RAID-5 parity engine can also check the data against its expected parity.

Abstract: A system and method for virtual memory management. A plurality of virtual memory pages having selectable page sizes are used to tailor memory allocations in a way which balances overallocation of memory against the number of entries saved in accessing that memory through the translation buffer. A library routine can act on the overallocated memory to hide memory requests from the operating system.

Abstract: A system and method for vectorizing a non-innermost loop of a nested loop. Iterative loops of a nested loop are analyzed to determine if they can be vectorized (vector legality). If more than one iterative loop can be vectorized, a selection criteria is applied to select the iterative loop which would provide the most return from vectorization (vector selection).

Abstract: A method and apparatus for conductively cooling daughter card assemblies mounted to either an air or liquid cooled computer circuit module wherein the module has a cold plate and at least one mother board adjacent the cold plate. The module carries a number of daughter assemblies thereon adjacent the mother board. Each daughter card assembly has at least one daughter board which carries a number of electronic components on an element side of the board. A cooling side is disposed opposite the element side on the board. A thermally conductive plate has an inner side facing the mother board and an outer side opposite the inner side. The inner side has one or more projecting members extending perpendicularly towards the mother board. The daughter board is parallel to and in conductive contact with one side of the conductive plate. The module cold plate has a number of upstanding spacers projecting toward the mother board.

Abstract: A multidimensional interconnection and routing apparatus for a parallel processing computer connects together possessing elements in a three-dimensional structure. The interconnection and routing apparatus includes a plurality of processing element nodes. A communication connects at least one of the processing elements with a host system. An interconnection network connects together the processing element nodes in an X, y, and Z dimension. The network includes communication paths connecting each of the plurality of processing elements to adjacent processing elements in the plus and minus directions of each of the X, Y, and Z dimensions.

Abstract: Address translation means for distributed memory massively parallel processing (MPP) systems include means for defining virtual addresses for processing elements (PE's) and memory relative to a partition of PE's under program control, means for defining logical addresses for PE's and memory within a three-dimensional interconnected network of PE's in the MPP, and physical addresses for PE's and memory corresponding to identities and locations of PE modules within computer cabinetry. As physical PE's are mapped into or out of the logical MPP, as spares are needed, logical addresses are updated. Address references generated by a PE within a partition in virtual address mode are converted to logical addresses and physical addresses for routing on the network.

Abstract: A method and apparatus for cooling high power integrated circuits mounted on a printed circuit board. The invention includes producing a cold plate adapted to receive the printed circuit board thereon. A series of thermal shims are produced in incremental varying thicknesses from a thermally conductive material. A gap between each integrated circuit and the cold plate is determined that would result when the plate and board are assembled. One of the thermal shims is selected for each gap, the thickness of each selected shim being dependent upon the gap for which it is selected. The shim is placed between the cold plate and the integrated circuit so that when the module is assembled, the gap is eliminated and a thermal conductive path between the cold plate and each circuit is created.

Abstract: An operating system (OS) of a data processor physically relocates segments of memory containing real addresses used by the operating system itself, which addresses must remain unaltered within the system. The system identifies a memory bank containing a source segment having such real addresses, quiesces the OS, and copies the source segment to a target memory module. A register identifying the real addresses stored in the target module is renamed to the addresses of source segment, and the OS resumes executing normal tasks. The data processing system may have multiple system modules each having processors, memory, and/or other components.

Abstract: A system and address method for extracting a PE number and offset from an array index. According to one aspect of the present invention, a processing element number is assigned to each processing element, a local memory address is assigned to each memory location and a linearized index is assigned to each array element in an array. The processing element number of the processing element in which a particular array element is stored is computed as a function of a linearized index associated with the array element and a distribution specification associated with the array. In addition, a local memory address associated with the array element is computed as a function of the linearized index and the distribution specification.

Abstract: A daughter card assembly which provides relatively high conductive heat transfer from the electronic components on the daughter board to either an air or liquid cooled cold plate of a computer circuit module. The daughter card assembly has a daughter board with a plurality of electronic elements carried on an element side of the board. The opposite side of the board is a cooling side. The daughter board has one or more sockets which are electrically connected to the electronic elements on the board. The socket is adapted to plug into a connector carried on a mother board of a circuit module. A thermally conductive plate is disposed adjacent to and in thermal conductive contact with the cooling side of the daughter board. The conductive plate has an inner side facing the circuit module and an outer side on the opposite side. The plate is adapted to be in thermal conductive contact with the module cold plate to dissipate heat generated by the memory elements.