Patents Assigned to Credence Systems Corporation
  • Patent number: 8649993
    Abstract: A device under test is divided into multiple test domains, and test conditions for each of the multiple test domains are defined separately, so that each test domain has its own test pattern, timing data, and other test conditions. Each test domain can start and stop independently, and run at different speeds. Further, triggers are used to specify how the tests executed in the different test domains interact and communicate with one another. Any test domain can generate or wait for a trigger from any other test domain. A test domain can wait for a trigger from a test domain in a CPU.
    Type: Grant
    Filed: September 12, 2006
    Date of Patent: February 11, 2014
    Assignee: Credence Systems Corporation
    Inventor: Lionel Gilet
  • Patent number: 8504867
    Abstract: A clock signal generator having first and second coarse delay circuits connected in series delays pulses of a reference signal having period TP to produce pulses of the clock signal. The first coarse delay circuit delays pulses of the reference signal with a delay resolution of TP/N seconds over a range spanning TP seconds to produce pulses of an output signal. The second coarse delay circuit delays pulses of the output signal of the first coarse delay circuit over a range spanning TP seconds with a delay resolution of TP/M seconds to provide pulses of the clock signal with a timing resolution of TP/(M*N) seconds when the integers N and M are relatively prime.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: August 6, 2013
    Assignee: Credence Systems Corporation
    Inventor: Eric B Kushnick
  • Patent number: 8295182
    Abstract: An efficient automated test system and method are presented. In one embodiment, an automated test system is implemented in a routed event distribution architecture. In one exemplary implementation, an automated test system includes a plurality of test instruments, a switched event bus, and a test controller component. The plurality of test instruments perform testing. The switched event bus communicatively couples the plurality of instruments. The switched event bus comprises an event distribution switch that flexibly routes event information across event lines of the switched event bus. The test controller controls the testing and the switched event bus.
    Type: Grant
    Filed: July 2, 2008
    Date of Patent: October 23, 2012
    Assignee: Credence Systems Corporation
    Inventors: James Jula, Kenneth Skala, Vicki L. Skala, legal representative, Jeffrey Currin
  • Publication number: 20110234271
    Abstract: A clock signal generator having first and second coarse delay circuits connected in series delays pulses of a reference signal having period TP to produce pulses of the clock signal. The first coarse delay circuit delays pulses of the reference signal with a delay resolution of TP/N seconds over a range spanning TP seconds to produce pulses of an output signal. The second coarse delay circuit delays pulses of the output signal of the first coarse delay circuit over a range spanning TP seconds with a delay resolution of TP/M seconds to provide pulses of the clock signal with a timing resolution of TP/(M*N) seconds when the integers N and M are relatively prime.
    Type: Application
    Filed: September 28, 2010
    Publication date: September 29, 2011
    Applicant: CREDENCE SYSTEMS CORPORATION
    Inventor: Eric B. Kushnick
  • Patent number: 7810005
    Abstract: A system and method for reducing timing errors in automated test equipment (ATE) offering increased data rates for the testing of higher-speed integrated circuits. Embodiments provide an effective mechanism for increasing the data rate of an ATE system by delegating processing tasks to multiple test components, where the resulting data rate of the system may approach the sum of the data rates of the individual components. Each component is able to perform data-dependent timing error correction on data processed by the component, where the timing error may result from data processed by another component in the system. Embodiments enable timing error correction by making the component performing the correction aware of the data (e.g., processed by another component) causing the error. The data may be shared between components using existing timing interfaces, thereby saving the cost associated with the design, verification and manufacturing of new and/or additional hardware.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: October 5, 2010
    Assignee: Credence Systems Corporation
    Inventors: Jean-Yann Gazounaud, Howard Maassen
  • Patent number: 7805628
    Abstract: A clock signal generator having first and second coarse delay circuits connected in series delays pulses of a reference signal having period Tp to produce pulses of the clock signal. The first coarse delay circuit delays pulses of the reference signal with a delay resolution of Tp/N seconds over a range spanning Tp seconds to produce pulses of an output signal. The second coarse delay circuit delays pulses of the output signal of the first coarse delay circuit over a range spanning Tp seconds with a delay resolution of TP/M seconds to provide pulses of the clock signal with a timing resolution of Tp/(M*N) seconds when the integers N and M are relatively prime.
    Type: Grant
    Filed: April 2, 2001
    Date of Patent: September 28, 2010
    Assignee: Credence Systems Corporation
    Inventor: Eric B. Kushnick
  • Patent number: 7765443
    Abstract: One embodiment of the invention is a portion of a test system that includes a timing generation circuit and a formatter that are coupled together, which are on a single CMOS (complementary metal oxide semiconductor) integrated circuit. The timing Generation circuit generates software words. The formatter receives the software words and provides a specified number of transitions per second and a specified edge placement resolution and accuracy. It is noted that the formatter includes a drive circuit and a response circuit. Specifically, the drive circuit includes a plurality of slices, where each slice receives an independent data stream and produces an independent formatted level. The response circuit includes a plurality of slices, where each slice receives an independent data stream and produces an independent strobe marker.
    Type: Grant
    Filed: May 7, 2004
    Date of Patent: July 27, 2010
    Assignee: Credence Systems Corporation
    Inventors: Ahmed Rashid Syed, Burnell G. West
  • Patent number: 7761751
    Abstract: A method and system for performing diagnosing in an automatic test environment. The method begins by determining a fail condition during a test of a device under test (DUT). A diagnostic suite is determined for testing the fail condition. The diagnostic suite is generated if the diagnostic suite is not available for access.
    Type: Grant
    Filed: February 20, 2007
    Date of Patent: July 20, 2010
    Assignee: Credence Systems Corporation
    Inventor: Burnell G. West
  • Publication number: 20100023294
    Abstract: An efficient automated testing system and method are presented. In one embodiment, an automated testing system includes a control component and an automated test instrument for testing a device or a plurality of devices (e.g., packages or wafers containing multiple independent different devices) under test. The automated test instrument component performs testing operation on the device or devices under test (DUT). The control component manages testing activities of a test instrument testing the device under test, including managing implementation of a plurality of test programs loaded as a group. In one exemplary implementation, the automated test system also includes a DUT interface and a user interface. The device under test interface interfaces with a device or devices under test.
    Type: Application
    Filed: August 28, 2008
    Publication date: January 28, 2010
    Applicant: CREDENCE SYSTEMS CORPORATION
    Inventors: Yung Daniel Fan, David N. Grant, Mark Hanbury Brown, Jonathan David Godfree Pryce
  • Patent number: 7627790
    Abstract: An integrated circuit tester channel includes an integrated circuit (IC) for adding a programmably controlled amount of jitter to a digital test signal to produce a DUT input signal having a precisely controlled jitter pattern. The IC also measures periods between selected edges of the same or different ones of the DUT output signal, the DUT input signal, and a reference clock signal. Additionally, when the DUT input and output signals convey repetitive patterns, the IC can measure the voltage of the DUT input out output signal as selected points within the pattern by comparing it to an adjustable reference voltage. Processing circuits external to the IC program the IC to provide a specified amount of jitter to the test signal, control the measurements carried out by the measurement circuit, and process measurement data to determine the amount of jitter and other characteristics of the DUT output signal, and to calibrate the jitter in the DUT input signal.
    Type: Grant
    Filed: November 18, 2004
    Date of Patent: December 1, 2009
    Assignee: Credence Systems Corporation
    Inventors: Arnold M. Frisch, Thomas Arthur Almy
  • Patent number: 7615990
    Abstract: An enhanced loadboard and method for enhanced automated test equipment (ATE) signaling. More specifically, embodiments provide an effective mechanism for reducing signal degradation and error interjection by replacing one or more relays with signal splitters for directing signals between one or more pins of a coupled ATE instrument, where the signal splitters reduce loadboard size and operating cost.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: November 10, 2009
    Assignee: Credence Systems Corporation
    Inventor: Masashi Shimanouchi
  • Patent number: 7532014
    Abstract: A method and apparatus for radio frequency vector calibration of s-parameter measurements to the tips of the wafer probe needles of an automatic test equipment production tester. The method involves a modified Line-Reflect-Line (LRL) calibration routine that uses a Thru-Reflect-Line to LRL shift to eliminate the need for a precisely characterized reflect standard used during a conventional LRL calibration. The method further involves de-embedding the non-ideal effects of the non-zero length thru standard used during the calibration routine to improve measurement accuracy of the tester. The apparatus may involve the use of RF relays to allow multiple wafer probe needles to share RF test ports.
    Type: Grant
    Filed: August 8, 2006
    Date of Patent: May 12, 2009
    Assignee: Credence Systems Corporation
    Inventors: Steffen Chladek, Martin Breinbauer
  • Publication number: 20090076761
    Abstract: An efficient automated test system and method are presented. In one embodiment, an automated test system is implemented in a routed event distribution architecture. In one exemplary implementation, an automated test system includes a plurality of test instruments, a switched event bus, and a test controller component. The plurality of test instruments perform testing. The switched event bus communicatively couples the plurality of instruments. The switched event bus comprises an event distribution switch that flexibly routes event information across event lines of the switched event bus. The test controller controls the testing and the switched event bus.
    Type: Application
    Filed: July 2, 2008
    Publication date: March 19, 2009
    Applicant: CREDENCE SYSTEMS CORPORATION
    Inventors: James Jula, Kenneth Skala, Jeffrey Currin, Vicky L. Skala
  • Patent number: 7496467
    Abstract: An integrated circuit testing device, such as an ATE, configured with an architecture comprising a distinct software layer and a distinct hardware layer with an interface for tester abstraction providing a communication conduit between the software layer and the hardware layer. The software layer communicates in device under test terms whereas the hardware layer communicates in the terms of the testing apparatus. Various communication interface points are provided to the software and hardware layers, as well as the interface for tester abstraction.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: February 24, 2009
    Assignee: Credence Systems Corporation
    Inventor: William A. Fritzsche
  • Patent number: 7492181
    Abstract: A method for determining an output voltage of a device under test is disclosed. In the method, a first voltage is placed onto a terminal of a resister that is coupled to the device under test and a first current is through the resistor that corresponds to the first voltage is measured. A second voltage is then placed onto the terminal of the resistor and a second current is measured through the resistor that corresponds to the second voltage. An actual resistance of the resistor is computed based on the difference between the first voltage and the second voltage divided by the difference between the first current and the second current. An output voltage of the device under test is calculated based on a magnitude of a measured current through the resistor when the terminal is grounded multiplied by a magnitude of the actual resistance of the resistor.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: February 17, 2009
    Assignee: Credence Systems Corporation
    Inventors: Laurence Crosby, John M. Oonk
  • Patent number: 7471100
    Abstract: A test head for an integrated circuit tester includes a main chassis defining a chamber that is open at the top. Tester modules are installed in the chamber, each tester module being removable as a unit from the chamber and including a tester module chassis, multiple pin electronics cards, and a tester module interface structure exposed at the top of the chamber. A test head interface structure is engageable with the tester module interface structures of the tester modules for connecting the tester module interface structures to a device interface unit.
    Type: Grant
    Filed: November 5, 2007
    Date of Patent: December 30, 2008
    Assignee: Credence Systems Corporation
    Inventors: Wayne H. Miller, Carlos R. Ramos, Peter S. Young
  • Patent number: 7471753
    Abstract: A clock synthesizer uses a serializer to convert a parallel data stream into clock signals. The frequency of the synthesized clock is dependent on the bit values of the parallel data stream and the frequency of the reference clock used by the serializer. Rapid tuning of the frequency is provided by changing the bit values of the parallel data stream. Fine tuning of the frequency is provided by changing the frequency of the reference clock. With this configuration, the clock device is capable of generating clock signals with very low jitter, is tunable to a very fine resolution in frequency, is able to skew to an external trigger with no glitches, and is able to hop to different frequencies with minimal delays. Moreover, the clock device can be designed at fairly low cost, because the serializer is widely available as a component in telecommunications applications.
    Type: Grant
    Filed: February 1, 2005
    Date of Patent: December 30, 2008
    Assignee: Credence Systems Corporation
    Inventor: Samuel Walker
  • Patent number: 7454678
    Abstract: A system and method for processing scan data for integrated circuit testing. Scan data is divided into three groups of scan data segments: scan-in data segments, scan-out data segments and scan-mask data segments. The sequence of scan data segments in each group constitutes the operative test data in a scan stream. Each scan stream is represented by a table having a row corresponding to each scan data segment in the stream. Each row has four fields: a start address, a segment length, a start pad length and an end pad length. Scan streams consist of the bit sequence of segment data interposed by dummy data corresponding in length to the start pad and end pad lengths. Scan streams are interleaved by using the pad lengths to time the processing of scan data segments.
    Type: Grant
    Filed: August 23, 2005
    Date of Patent: November 18, 2008
    Assignee: Credence Systems Corporation
    Inventors: Jamie S. Cullen, Burnell G. West
  • Patent number: 7439728
    Abstract: A system and method for calibration of a test socket using a composite waveform. A group of input signal pins of test system are coupled together. A pin belonging to the group is selected as a pin under calibration. A first calibration edge is applied to the pin under calibration. After a delay, a group of complementary edges is applied to the remaining pins of the group. As a result of the coupling of the pins, a response comprising a reflected edge and a transmitted combined edge are produced, which overlap to form a composite waveform. A comparator is used to detect an observable feature in the composite waveform to obtain timing information with respect to the pin under calibration and the remaining pins of the group. Each pin may be analyzed in turn, and the group of pins calibrated using the acquired information.
    Type: Grant
    Filed: July 19, 2005
    Date of Patent: October 21, 2008
    Assignee: Credence Systems Corporation
    Inventor: Robert L. Hickling
  • Patent number: 7430130
    Abstract: A switching converter produces an output signal transmitted to a variable load impedance to produce a load voltage VDD across the load impedance and holds VDD close to a set point voltage VSP selected by control data DREF1 to compensate for variations in the load impedance which tend to drive VDD away from VSP. The switching converter includes a pulse-width modulated power converter for producing the output signal of voltage VOUT in response to an input signal of voltage VIN, wherein a ratio VOUT/VIN is a function of a duty cycle D1 of a pulse-width modulated signal VPWM1. A pulse-width modulation circuit generates the VPWM signal of duty cycle D1 controlled by a control signal, and a feedback control circuit monitoring the load voltage VDD adjusts D1 to keep the load voltage as close as possible to VSP. A power source supplies the input signal of voltage VIN to the power converter.
    Type: Grant
    Filed: May 18, 2006
    Date of Patent: September 30, 2008
    Assignee: Credence Systems Corporation
    Inventor: William Devey