Abstract: An optical receiver is provided, which includes a housing, an objective lens situated in the housing, a solid immersion lens (SIL) mounted onto the housing, and thermal management element affixed to the housing to control the temperature of the SIL. The thermal management element may be a coolant conduit, a thermoelectric cooling (TEC) device, etc. A coolant spray may also be provided to spray the imaged specimen.

Abstract: A test head for an integrated circuit tester includes a main chassis defining a chamber that is open at the top. Tester modules are installed in the chamber, each tester module being removable as a unit from the chamber and including a tester module chassis, multiple pin electronics cards, and a tester module interface structure exposed at the top of the chamber. A test head interface structure is engageable with the tester module interface structures of the tester modules for connecting the tester module interface structures to a device interface unit.

Abstract: The invention concerns a column for producing a focused particle beam comprising: a device (100) focusing particles including an output electrode (130) with an output hole (131) for allowing through a particle beam (A); an optical focusing device (200) for simultaneously focusing an optical beam (F) including an output aperture (230). The invention is characterized in that said output aperture (230) is transparent to the optical beam (F), while said output electrode (130) is formed by a metallic insert (130) maintained in said aperture (230) and bored with a central hole (131) forming said output orifice.

Abstract: An apparatus for testing electronic devices employs a programmable device to adjust the timing of the strobes such that the strobes sample the bit stream from a device under test at or near the center of the bit position. The strobe time adjustment is performed based on pairs of strobe readings made around a number of different bit positions. The programmable device examines the pairs of strobe reading made around each of the different bit positions to determine whether or not a bit transition has occurred there. The programmable device selects the bit positions around which a bit transition has not occurred as eye candidates, and defines the center of the largest contiguous region of eye candidates as the center of the bit position.

Abstract: A power supply assembly includes a dielectric substrate and a power supply circuit supported by the dielectric substrate. A conductive connection block is attached to the dielectric substrate at a main surface thereof and is connected to a power supply terminal of the power supply circuit. A spring probe pin is fitted in a bore formed in the connection block and includes a conductive sleeve and a conductive plunger fitted in the sleeve. The conductive sleeve is in electrically conductive contact with the connection block.

Abstract: Time-resolved emission can be used to measure loop-synchronous, small-signal voltage perturbation in integrated circuits. In this technique the measurements are completely non-invasive and so reflect the true device behavior. The time-dependant propagation delay caused by Vdd modulation also shows the expected qualitative signature. This technique should find applications in circuits with relatively fast clock-like circuits where loop-synchronous voltage pickup is limiting circuit behavior.

Abstract: A phase locked loop circuit (PLL) has a reference terminal for receiving a reference signal and an output terminal for providing an output signal.

Abstract: A system for probe-less non-invasive detection of electrical signals from integrated circuit devices is disclosed. The system includes an illumination source, collection optics, imaging optics, and a photon sensor. In a navigation mode, the light source is activated and the imaging optics is used to identify the target area on the chip and appropriately position the collection optics. Once the collection optics is appropriately positioned, the light source is deactivated and the photon sensor is used to detect photons emitted from the chip. No mention of cooling (active device measurement capability) and advanced optics to detect the features (SIL).

Abstract: A bi-convex solid immersion lens is disclosed, having a top and bottom convex surfaces. The radius of curvature of the bottom surface is larger than that of the top surface. A conical sloped side-wall connects the top and bottom surface.

Abstract: An apparatus and method for tracing back a probing location to identify the circuit element being probed on a device under test (DUT). The coordinates of the irregularity on the DUT are used to trace back to the logic cone to decipher the root-cause of the irregularity. The Def and Lef files are interrogated using the coordinates to obtain the cell and net data to enable the investigation. Additionally, a schematic viewer is used to investigate the logic cone to potential root-causes for the irregularities.

Abstract: A method and apparatus for adding fill-in clock pulses to an analog to digital converters input clock signal between requests for analog data acquisition. The circuit that provides the fill-in clock pulses is able to detect a request for analog data acquisition, synchronously stop adding fill-in clock pulses, and track the request for data acquisition.

Abstract: A method for identifying an area of a chip to be probed proceeds as follows. A callout list of failures is obtained from a tester, the list including cell name and pin for each failure. A Def file is interrogated to locate a Def entry matching the cell name, and a cell type, cell location, and cell orientation data is obtained for the cell from the Def file. A Lef file is then interrogated to locate a Lef entry matching the cell type, and the coordinates of the pin are obtaining from the Lef file. A GDS file is interrogated to locate a GDS entry matching the cell type, and the coordinates of polygons listed in the GDS entry are obtained. The coordinates of the pin are then crossed with the coordinates of the polygons to identify overlapping area. The overlapping area is defined as the location to be probed. A driving signal is applied to a stage to align a prober with the location to be rprobed.

Abstract: An apparatus and method for tracing back a probing location to identify the circuit element being probed on a device under test (DUT). The coordinates of the irregularity on the DUT are used to trace back to the logic cone to decipher the root-cause of the irregularity. The Def and Lef files are interrogated using the coordinates to obtain the cell and net data to enable the investigation. Additionally, a schematic viewer is used to investigate the logic cone to potential root-causes for the irregularities.

Abstract: An integrated FIB/PEM apparatus and method for performing failure analysis on integrated circuits. In-situ failure analysis is enabled by integrating Photon Emission Microscopy into a Focused Ion Beam system, thereby improving throughput and efficiency of Failure Analysis. An iterative method is described for identifying and localizing fault sites on the circuit.

Abstract: A device under test is divided into multiple test domains, and test conditions for each of the multiple test domains are defined separately, so that each test domain has its own test pattern, timing data, and other test conditions. Each test domain can start and stop independently, and run at different speeds. Further, triggers are used to specify how the tests executed in the different test domains interact and communicate with one another. Any test domain can generate or wait for a trigger from any other test domain (including the CPU).

Abstract: A method for identifying an area of a chip to be probed proceeds as follows. A callout list of failures is obtained from a tester, the list including cell name and pin for each failure. A Def file is interrogated to locate a Def entry matching the cell name, and a cell type, cell location, and cell orientation data is obtained for the cell from the Def file. A Lef file is then interrogated to locate a Lef entry matching the cell type, and the coordinates of the pin are obtaining from the Lef file. A GDS file is interrogated to locate a GDS entry matching the cell type, and the coordinates of polygons listed in the GDS entry are obtained. The coordinates of the pin are then crossed with the coordinates of the polygons to identify overlapping area. The overlapping area is defined as the location to be probed. A driving signal is applied to a stage to align a prober with the location to be probed.

Abstract: The present invention relates to test systems for testing integrated circuit devices and to calibration associated systems and methods. One embodiment of the invention provides an auto-calibration system. The system includes: a plurality of delay line elements (DLEs) adapted to be connected in a loop; a state machine coupled to the plurality of DLEs and operative to provide state data for the plurality of DLEs; a start oscillation signal receiving circuit coupled to the loop and operative to trigger the loop in response to receipt of a start oscillation signal; and a calibration circuit coupled to the loop and operative to acquire calibration data for the plurality of DLEs.

Abstract: An integrated circuit tester for testing an IC device under test (DUT) during a succession of test cycles includes a pattern generator programmed to generate data before each test cycle encoded to specify all test activities to be carried out during the test cycle and to specify for each test activity a time during the test cycle at which the test activity is to be carried out and a DUT IO pin at which the test activity is to be carried out. Multiple programmable tester channels each comprise multiple DUT interface circuits, each of which can be connected to a separate DUT IO pin for carrying out test activities at that DUT IO pin when signaled to do so, and hardware resources programmed by decoding instructions to decode the data from the pattern generator for each test cycle and initiate each specified test activity by signaling the DUT interface circuit that is specified for the test activity at the time specified for the test activity.

Abstract: A charged particle beam system and scanning control method capable of imaging, and possibly editing, a device under test (DUT). The charged particle beam system contains a charged particle beam generation unit, such as a focused ion beam (FIB) column, which emits a charged particle beam onto the DUT. Also included is a scan controller arrangement implementing a finite state machine to control the application of the charged particle beam onto the DUT according to a plurality of scanning control parameters. The scanning control parameters may describe one or more scan regions that are rectangular in shape. Further, the parameters may describe one or more scan regions describing other shapes by way of a bit-map. Similarly, a method for controlling the scanning of a charged particle beam that involves obtaining a set of scanning control parameters, and then directing the charged particle beam as specified by the scanning control parameters by way of a finite state machine, is disclosed.

Abstract: A system and method for automatically and accurately determining the exact location of a knife-edge, such as an edge of an optical shutter, so that it can be controlled automatically. In one aspect the system comprises a mechanized shutter coupled to a shutter controller that can automatically control the shutter's location and movement. According to one implementation of the shutter controller the system takes a first image at a first shutter position. The shutter is then moved a predetermined about and a second image is taken. Then, the pixels of each image are added in the direction perpendicular to the movement of the shutter, so as to provide two one-dimension functions. A linear difference of the functions is then taken, so as to obtain a one-dimensional linear difference function. A peak in the linear difference function is then identified as the location of the shutter.