Abstract: A landing system is provided for accurate placing of collection optics in a microscope. In one example, a solid immersion lens (SIL) is used for light collection, and the landing system is operated to place the SIL in contact with an IC. A proximity sensor is used for determining the SIL's position with respect to the IC. The arrangement is attached to a z-motion stage. During the placement procedure, the navigation is performed in steps and at each step the compression of the SIL is measured relative to its uncompressed state. When a measured compression exceeds a preset threshold, a SIL landing is recognized. In one example, after a landing is recognized, a further compression is imparted to the SIL in order to place the SIL in a focusing distance to the objective lens.

Abstract: A method for improved ATE (automatic test equipment) timing calibration at a DUT (device under test). The method includes step of accessing a DUT component using an ATE component and performing physical calibration on a first portion of signal pathways coupling the ATE component to the DUT component. A simulation based calibration is performed on a second portion of signal pathways coupling the ATE component to the DUT component. The physical calibration results are combined with simulation based calibration results to calibrate timing propagation delay between the ATE component and the DUT component.

Abstract: Apparatus and processes are disclosed for milling copper adjacent to organic low-k dielectric on a substrate by directing a charged-particle beam at a portion of the copper and exposing the copper to a precursor sufficient to enhance removal of the copper relative to removal of the dielectric, wherein the precursor contains an oxidizing agent, has a high sticking coefficient and a long residence time on the copper, contains atoms of at least one of carbon and silicon in amount sufficient to stop oxidation of the dielectric, and contains no atoms of chlorine, bromine or iodine. In one embodiment, the precursor comprises at least one of the group consisting of NitroEthanol, NitroEthane, NitroPropane, NitroMethane, compounds based on silazane such as HexaMethylCycloTriSilazane, and compounds based on siloxane such as Octa-Methyl-Cyclo-Tetra-Siloxane. Products of the processes are also disclosed.

Abstract: A method for utilizing interference fringe patterns generated when milling a trench through a semiconductor substrate by a method such as FIB milling, to determine and optimize the thickness uniformity of the trench bottom. The interference fringes may be mapped and the mapping used to direct the FIB milling to those regions which are thicker to correct observed non-uniformities in the trench floor thickness by varying the pixel dwell time across the milled area. The interference fringe mapping may be used to develop computerized contour lines to automate the pixel dwell time variations as described above, for correcting non-uniformities in the trench floor thickness. The method may be applied to applications other than trench formation for backside editing, such as monitoring progress in forming a milled object.

Abstract: An integrated circuit testing device, such as an ATE, configured with an architecture comprising a distinct software layer and a distinct hardware layer with an interface for tester abstraction providing a communication conduit between the software layer and the hardware layer. The software layer communicates in device under test terms whereas the hardware layer communicates in the terms of the testing apparatus. Various communication interface points are provided to the software and hardware layers, as well as the interface for tester abstraction.

Abstract: A circuit and related method for distributing events in an event stream (i.e., an electronic signal having a plurality of rising edge transitions and falling edge transitions). The circuit distributes the events in a primary event stream across multiple secondary event streams in such a way that the event rate in each of the secondary event streams is lower than the event rate in the primary event stream, but the relative timing of the events in the primary event stream is maintained in each of the secondary event streams. The secondary event streams can then be provided to respective timestamp circuits, which record the times at which events occur in the secondary event streams. Since the relative timing of the events in the primary event stream is maintained in each of the secondary event streams, the multiple timestamp circuits collectively record the times at which events occur in the primary event stream. The circuit and related method can be used when debugging/testing semiconductor devices.

Abstract: Methods, apparatus and data structures useful in correcting PICA image data are described. An exemplary method comprises acquiring optical image data of a target having identifiable optical-image features, acquiring PICA image data of the target having identifiable PICA-image features corresponding to the optical-image features, matching PICA-image features with corresponding optical-image features, and calculating from matched PICA-image features and optical-image features a set of coefficients defining relationships between observed positions of PICA-image features and optical-image features. Corrections are applied to the observed positions of detected photons based on the coefficients. The coefficients may provide a local correction using a bilinear relationship giving the transformation of a rectangle formed by four features of the PICA-image data to fit a corresponding rectangle in the optical-image data.

Abstract: An integrated circuit testing device, such as an ATE, configured with an architecture comprising a distinct software layer and a distinct hardware layer with an interface for tester abstraction providing a communication conduit between the software layer and the hardware layer. The software layer communicates in device under test terms whereas the hardware layer communicates in the terms of the testing apparatus. Various communication interface points are provided to the software and hardware layers, as well as the interface for tester abstraction.

Abstract: An integrated circuit testing device, such as an ATE, configured with an architecture comprising a distinct software layer and a distinct hardware layer with an interface for tester abstraction providing a communication conduit between the software layer and the hardware layer. The software layer communicates in device under test terms whereas the hardware layer communicates in the terms of the testing apparatus. Various communication interface points are provided to the software and hardware layers, as well as the interface for tester abstraction.

Abstract: A package optimized for thinning of an attached semiconductor die. The package comprises an extension ring attached to a bottom surface of the package, and a die carrier plate attached to the extension ring for receiving a semiconductor die. The die carrier plate may be attached to the extension ring by an adhesive that permits removal of the carrier plate from the semiconductor die and extension ring by a small applied force after encapsulation of the semiconductor die. The encapsulant may include a filler material for modifying properties such as hardness, thermal coefficient of expansion, thermal conductivity. The materials used for the extension ring and encapsulant may be selected for compatibility with the die lapping operation.

Abstract: A method for linking compiled pattern data and loading the data into tester hardware includes the steps of generating a composite object that includes a shared resource, determining a local shared resource specific to a test instrument that is associated with the shared resource in the composite object, assigning a local reconciled value or address to the local shared resource, and loading the local shared resource into the test instrument.

Abstract: A test apparatus has multiple instruments that are synchronized with respect to one another so that test data generated by them arrive at the pins of a device under test at the time specified in a test program. The synchronization of the multiple instruments is carried out by introducing delays to triggers that are generated and used by the multiple instruments. The amount of delay that is introduced varies from instrument to instrument and is based on differences in the actual transmission and processing delays and clock rates.

Abstract: An apparatus and method for processing an integrated circuit employing optical interference fringes. During processing, light is directed on the integrated circuit and based upon the detection of interference fringes, further processing may be controlled. One implementation involves charged particle beam processing of an integrated circuit as function of detection of interference fringes. A charged particle beam trench milling operation is performed in or on the substrate of an integrated circuit. Light is directed on the floor of the trench. When the floor approaches the underlying circuit structures, some light is reflected from the floor of the trench and some light penetrates the substrate and is reflected off the underlying circuit structures. Interference fringes may be formed from the constructive or destructive interference between the light reflected from the floor and the light from the circuit structures. Processing may be controlled as function of the detection of interference fringes.

Abstract: A system, apparatus, and method for analyzing photon emission data to discriminate between photons emitted by transistors and photons emitted by background sources. The analysis involves spatial and/or temporal correlation of photon emissions. After correlation, the analysis may further involve obtaining a likelihood that the correlated photons were emitted by a transistor. After correlation, the analysis may also further involve assigning a weight to individual photon emissions as a function of the correlation. The weight, in some instances, reflecting a likelihood that the photons were emitted by a transistor. The analysis may further involve automatically identifying transistors in a photon emission image.

Abstract: A test head for a semiconductor integrated circuit tester, the test head includes a power supply board mounted to a power distribution board and positioned between the power distribution board and a device interface board. The power supply board includes a power supply circuit having power supply input terminals for receiving electrical power at a voltage Vin and force and return terminals for supplying regulated electrical power at a voltage Vout. The power supply board further includes a power connector for connecting the force and return terminals of the power supply circuit to power supply contact elements of the device interface board.

Abstract: Method and apparatus for optically testing (e.g., using a laser beam) an operating integrated circuit (device under test—DUT) that actively control the operating temperature of the DUT. This is chiefly useful with flip-chip packaged ICs. The temperature of the DUT varies with its operating power consumption, and this fluctuation in temperature adversely affects the results obtained during optical probing or other optical testing. Furthermore, the DUT may be damaged if its temperature exceeds design limits. The temperature of the DUT is controlled by thermally contacting the exposed backside surface of the DUT die to a diamond film heat conductor, an associated heat sink structure, and at least one thermoelectric device. The thermoelectric device is controlled by a temperature sensor proximal to the DUT. By controlling the amount and direction of the electrical current supplied to the thermoelectric device in response to the sensed temperature, the temperature of the DUT is maintained.

Abstract: Apparatus and processes are disclosed for milling copper adjacent to organic low-k dielectric on a substrate by directing a charged-particle beam at a portion of the copper and exposing the copper to a precursor sufficient to enhance removal of the copper relative to removal of the dielectric, wherein the precursor contains an oxidizing agent, has a high sticking coefficient and a long residence time on the copper, contains atoms of at least one of carbon and silicon in amount sufficient to stop oxidation of the dielectric, and contains no atoms of chlorine, bromine or iodine. In one embodiment, the precursor comprises at least one of the group consisting of NitroEthanol, NitroEthane, NitroPropane, NitroMethane, compounds based on silazane such as HexaMethylCycloTriSilazane, and compounds based on siloxane such as Octa-Methyl-Cyclo-Tetra-Siloxane. Products of the processes are also disclosed.

Abstract: A system for testing an integrated circuit device under test (DUT) communicating though synchronous digital signals and through a high speed serialization/de-serialization (serdes) bus includes a serdes interface circuit for communicating with the DUT via the serdes bus and an integrated circuit (IC) tester for communicating with the DUT and with the serdes interface circuit via digital signals. State changes in the digital signals are synchronized to a clock signal within the IC tester. The serdes interface circuit receives instructions from the IC tester via at least one of the digital signals and responds to the instructions by transmitting data to the DUT via the serdes bus using appropriate serdes protocol, by receiving and storing data transmitted by the DUT via the serdes bus, and by thereafter forwarding the stored data to the IC tester via at least one of the digital signals.

Abstract: An interface structure for use in a semiconductor integrated circuit tester for connecting a test head interface to a DUT interface includes a first frame member having first and second opposite main faces, a second frame member having first and second opposite main faces, and a spacer securing the first and second frame members together in spaced relationship. A first cable assembly header is received in an aperture of the first frame member and includes a conductive element and electrically conductive terminal members exposed at a main face of the first frame member and electrically insulated from the conductive element of the first header. A second cable assembly header is received in an aperture of the second frame member and includes a conductive element and electrically conductive terminal members exposed at a main face of the second frame member and electrically insulated from the conductive element of the second header.

Abstract: An integrated circuit (IC) tester includes a set of power modules mounted in a test head, each contacting a device interface board (DIB). The DIB provides power paths for delivering an output current generate by each power module to a power input terminals of one or more IC devices under test (DUTs). Power modules that supply current to the same set of DUTs communicate with one another though conductive paths provided by the DIB to ensure that all power modules begin supplying load current to that set of DUTs at the same time and to ensure that all power modules supply substantially the same amount of load current to those DUTs.