Patents Assigned to Credence Systems Corporation
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Publication number: 20060108997Abstract: A system, apparatus, and method for analyzing photon emission data to discriminate between photons emitted by transistors and photons emitted by background sources. The analysis involves spatial and/or temporal correlation of photon emissions. After correlation, the analysis may further involve obtaining a likelihood that the correlated photons were emitted by a transistor. After correlation, the analysis may also further involve assigning a weight to individual photon emissions as a function of the correlation. The weight, in some instances, reflecting a likelihood that the photons were emitted by a transistor. The analysis may further involve automatically identifying transistors in a photon emission image.Type: ApplicationFiled: December 8, 2005Publication date: May 25, 2006Applicant: Credence Systems CorporationInventors: Romain Desplats, Patricia Le Coupanec, William Lo, Philippe Perdu, Steven Kasapi
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Patent number: 7049593Abstract: A single-photon detector includes a superconductor strip biased near its critical current. The superconductor strip provides a discernible output signal upon absorption of a single incident photon. In one example, the superconductor is a strip of NbN (niobium nitride). In another example, the superconductor strip meanders to increase its probability of receiving a photon from a light source. The single-photon detector is suitable for a variety of applications including free-space and satellite communications, quantum communications, quantum cryptography, weak luminescence, and semiconductor device testing.Type: GrantFiled: October 19, 2004Date of Patent: May 23, 2006Assignees: Credence Systems Corporation, University of RochesterInventors: Roman Sobolewski, Grigory N. Gol'tsman, Alexey D. Semenov, Oleg V. Okunev, Kenneth R. Wilsher, Steven A. Kasapi
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Patent number: 7045791Abstract: The invention concerns a column for producing a focused particle beam comprising: a device (100) focusing particles including an output electrode (130) with an output hole (131) for allowing through a particle beam (A); an optical focusing device (200) for simultaneously focusing an optical beam (F) including an output aperture (230). The invention is characterized in that said output aperture (230) is transparent to the optical beam (F), while said output electrode (130) is formed by a metallic insert (130) maintained in said aperture (230) and bored with a central hole (131) forming said output orifice.Type: GrantFiled: March 19, 2001Date of Patent: May 16, 2006Assignees: Credence Systems Corporation, Orsay-Physics, S.A.Inventors: Gérard Benas-Sayag, Patrick Bouchet, Antoine Corbin, Pierre Sudraud
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Patent number: 7042239Abstract: A semiconductor integrated circuit tester includes a housing having a main housing wall formed with an opening. A tester interface unit is located partially in the housing and incorporates an electrical connector segment that extends partially from the main housing wall for engaging an electrical connector segment of a device interface unit. A pusher member is located partially within the housing and is movable relative to the main housing wall between an extended position and a retracted position. In the extended position the pusher member projects from the opening in the main housing wall. An actuator is accessible at the exterior of the housing and is coupled to the pusher member for moving the pusher member between its retracted position and its extended position.Type: GrantFiled: June 25, 2004Date of Patent: May 9, 2006Assignee: Credence Systems CorporationInventor: Wayne H. Miller
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Patent number: 7042563Abstract: A method and system of testing integrated circuits (IC) via optical coupling. The optical system includes an optical fiber, fixture and focusing element. In addition, channels are provided in the fixture mounted on the integrated circuit to accommodate the optical system. The fixture acts as a heat sink. As such, one or more photosensitive elements/targets on the integrated circuit are probed using light that is brought to a focus on each target site. The light causes latching of data into the integrated circuit (which is operating under influence of a test program) and formation of a test pattern output from the integrated circuit that is used to confirm proper functioning of the IC.Type: GrantFiled: January 24, 2005Date of Patent: May 9, 2006Assignee: Credence Systems CorporationInventors: Kenneth R. Wilsher, Steven Kasapi
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Patent number: 7043390Abstract: Method and apparatus for circuit testing with ring-connected test instrument modules. A system for controlling one or more test instruments to test one or more integrated circuits includes a master clock and a controller. The test instruments are connected to form a communication ring. The master clock is connected to each test instrument and provides a clock signal to the one or more test instruments. The controller is connected to the communication ring and is configured to align counters of test instruments to derive a common clock time value from the clock signal. The controller is further configured to generate and send data words into the communication ring to carry the data words to each test instrument. The data words includes at least one data word specifying a test event to be performed, a common clock time value, and at least one of the test instruments.Type: GrantFiled: December 21, 2004Date of Patent: May 9, 2006Assignee: Credence Systems CorporationInventors: Michael F. Jones, Frederic Giral, William A. Fritzsche
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Patent number: 7042647Abstract: A scanned optical system for use in optical probing applications provides a large Field of View (FOV) for objective lenses having high Numerical Aperture (NA), such as Solid Immersion Lenses (SIL's). This enables high resolution imaging of semiconductor devices for such applications as laser probing, TIVA/LIVA, OBIRCH, and photon emission timing analysis. A hybrid scanning optics configuration is disclosed to provide high resolution imaging over a small area along with low resolution imaging over a large area.Type: GrantFiled: October 2, 2003Date of Patent: May 9, 2006Assignee: Credence Systems CorporationInventor: William K. Lo
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Patent number: 7039841Abstract: An apparatus for testing an integrated circuit includes a sequence control logic unit having an output channel connectable to an input pin of a device under test, a first memory to store a first instruction set comprising instructions executable by the sequence control logic unit, and a second memory to store a second instruction set comprising instructions executable by the sequence control logic unit, wherein at least one of the first memory and the second memory comprises a memory accessible in a non-sequential fashion.Type: GrantFiled: May 8, 2003Date of Patent: May 2, 2006Assignee: Credence Systems CorporationInventors: Jamie S. Cullen, Kris Sakaitani
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Patent number: 7038442Abstract: A system, apparatus, and method for analyzing photon emission data to discriminate between photons emitted by transistors and photons emitted by background sources. The analysis involves spatial and/or temporal correlation of photon emissions. After correlation, the analysis may further involve obtaining a likelihood that the correlated photons were emitted by a transistor. After correlation, the analysis may also further involve assigning a weight to individual photon emissions as a function of the correlation. The weight, in some instances, reflecting a likelihood that the photons were emitted by a transistor. The analysis may further involve automatically identifying transistors in a photon emission image.Type: GrantFiled: January 20, 2005Date of Patent: May 2, 2006Assignee: Credence Systems CorporationInventors: Romain Desplats, Patricia Le Coupanec, William K. Lo, Philippe Perdu, Steven Kasapi
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Patent number: 7034520Abstract: A product change tool for selectively engaging a product change element with an IC tester interface and disengaging the product change element from the tester interface includes a mobile frame mounted to a base frame and constrained to move relative to the base frame along an axis of linear movement, and a force mechanism for urging the mobile frame to move along the axis of linear movement relative to the base frame. The force mechanism includes first and second links pivotally connected together at their proximal ends and secured at their distal ends to the mobile frame and the base frame respectively. The distal ends of the links are spaced apart along the axis of linear movement and the proximal ends of the links are between the distal ends relative to that axis.Type: GrantFiled: September 9, 2005Date of Patent: April 25, 2006Assignee: Credence Systems CorporationInventors: Wayne H. Miller, Chris S. Paretich, James K. Lubin, Stuart M. Firestone
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Patent number: 7035755Abstract: Method and apparatus for circuit testing with ring-connected test instrument modules. A system for controlling one or more test instruments to test one or more integrated circuits includes a master clock and a controller. The test instruments are connected to form a communication ring. The master clock is connected to each test instrument and provides a clock signal to the one or more test instruments. The controller is connected to the communication ring and is configured to align counters of test instruments to derive a common clock time value from the clock signal. The controller is further configured to generate and send data words into the communication ring to carry the data words to each test instrument. The data words includes at least one data word specifying a test event to be performed, a common clock time value, and at least one of the test instruments.Type: GrantFiled: August 16, 2002Date of Patent: April 25, 2006Assignee: Credence Systems CorporationInventors: Michael F. Jones, Robert Whyte, Jamie S. Cullen, Naveed Zaman, Yann Gazounaud, Burnell G. West, William Fritzsche
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Patent number: 7036109Abstract: Methods and apparatus for integrated circuit diagnosis, characterization or modification using a focused ion beam. A method for editing an integrated circuit includes acquiring an image of structures of an integrated circuit by applying a focused ion beam to an outer surface of the integrated circuit to visualize structures beneath the outer surface of the integrated circuit. The method includes using the image to find a location of a circuit element in the integrated circuit and then performing one or more editing operations on the circuit element by applying a focused ion beam to the location found.Type: GrantFiled: October 17, 2002Date of Patent: April 25, 2006Assignee: Credence Systems CorporationInventors: Chun-Cheng Tsao, Theodore R. Lundquist, William Thompson, Erwan Le Roy, Eugene A. Delenia
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Publication number: 20060079086Abstract: Localized trenches or access holes are milled in a semiconductor substrate to define access points to structures of an integrated circuit intended for circuit editing. A conductor is deposited, such as with a focused ion beam tool, in the access holes and a localized heat is applied to the conductor for silicide formation, especially at the boundary between a semiconductor structure, such as diffusion regions, and the deposited conductor. Localized heat may be generated at the target location through precise laser application, current generation through the target location, or a combination thereof.Type: ApplicationFiled: October 12, 2004Publication date: April 13, 2006Applicant: Credence Systems CorporationInventors: Christian Boit, Theodore Lundquist, Chun-Cheng Tsao, Uwe Kerst, Stephan Schoemann, Peter Sadewater
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Publication number: 20060076503Abstract: An optical coupling apparatus for a dual column charged particle beam tool allowing both optical imaging of an area of an integrated circuit, as well as localized heating of the integrated circuit to form silicide. In one embodiment, optical paths from a whitelight source and a laser source are coupled together by way of first and second beam splitters so that a single optical port of the dual column tool may be utilized for both imaging and heating. In another embodiment, a single laser source is employed to provide both illumination for standard microscopy-type imaging, as well as localized heating. In a third embodiment, a single laser source provides heating along with localized illumination for confocal scanning microscopy-type imaging.Type: ApplicationFiled: September 8, 2005Publication date: April 13, 2006Applicant: Credence Systems CorporationInventor: Chun-Cheng Tsao
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Patent number: 7019546Abstract: A test head for a semiconductor integrated circuit tester includes first and second card cages and first and second groups of interface connectors for engagement by DUT edges of pin electronics cards installed in the first and second card cages respectively. The interface connectors of the first group are inclined at an angle less than 180° to the interface connectors of the second group.Type: GrantFiled: June 25, 2004Date of Patent: March 28, 2006Assignee: Credence Systems CorporationInventor: Wayne H. Miller
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Patent number: 7017091Abstract: A test system formatter may include a programmable drive circuit configurable to operate in any of a plurality of drive modes, each mode corresponding to a different combination of drive signals or drive timing markers or both, and a programmable response circuit configurable to operate in any of a plurality of strobe modes, each strobe mode corresponding to a different combination of strobe signals. The formatter may also include multiple drive channels and/or multiple response channels, each channel being formed, e.g., of an event logic interface and a corresponding linear delay element. The drive channels provide signals to the drive circuit to be used to generate drive signals or drive timing markers or both. The response channels receive from one or more pin-electronics comparators response signals used to generate fail outputs. The programmable drive and response circuits are configurable to route signals through multiple channels in parallel.Type: GrantFiled: March 18, 2002Date of Patent: March 21, 2006Assignee: Credence Systems CorporationInventor: Burnell G. West
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Patent number: 7012537Abstract: A beacon circuit enabling study of active elements in an integrated circuit is disclosed. The beacon circuit may be integral to a DUT to be tested. The DUT is stimulated by a conventional ATE, so that its active devices are operating. The signal from the active device is sent to the beacon circuit which, in response to the signal, emits light having intensity that is proportional to the value of the signal. In one example, the beacon circuit is constructed as a voltage to current converter having its input connected to the node of interest and its output connected to a current to light converter. In one example, the current to light converter is implemented as a current mirror circuit. One beneficial implementation disclosed is the use of the beacon circuit for the study of voltage supply disturbances.Type: GrantFiled: May 14, 2004Date of Patent: March 14, 2006Assignee: Credence Systems CorporationInventors: Gary Leonard Woods, Steven Kasapi
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Patent number: 7009173Abstract: An integrated housing for a lens and a photodetector, which is being cooled to low temperatures to enable the detector to detect faint emission of photons. An enclosure is provided to which a lens is affixed from one side using a retaining ring, and a photodetector is affixed from the opposite side. The enclosure is affixed to a TE cooler. The enclosure and the retaining ring are made from materials having similar thermal expansion coefficients.Type: GrantFiled: June 22, 2004Date of Patent: March 7, 2006Assignee: Credence Systems CorporationInventors: Radu Ispasoiu, Thomas R. Gockel, James S. Vickers
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Patent number: 7009382Abstract: A system and method for calibration of a test socket using a composite waveform. A group of input signal pins of test system are coupled together. A pin belonging to the group is selected as a pin under calibration. A first calibration edge is applied to the pin under calibration. After a delay, a group of complementary edges is applied to the remaining pins of the group. As a result of the coupling of the pins, a response comprising a reflected edge and a transmitted combined edge are produced, which overlap to form a composite waveform. A comparator is used to detect an observable feature in the composite waveform to obtain timing information with respect to the pin under calibration and the remaining pins of the group. Each pin may be analyzed in turn, and the group of pins calibrated using the acquired information.Type: GrantFiled: December 4, 2003Date of Patent: March 7, 2006Assignee: Credence Systems CorporationInventor: Robert L. Hickling
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Patent number: 6998863Abstract: A test head for a semiconductor integrated circuit tester, the test head includes a housing, a backplane structure attached to the housing in a manner permitting pivotal movement of the backplane structure relative to the housing, and a latch mechanism for forcing the backplane structure towards its closed position. The latch mechanism includes a cam follower that projects from the backplane structure in a direction perpendicular to the axis of pivotal movement of the backplane structure, a cam plate that is attached to the housing and is moveable relative to the housing and is formed with a cam slot for receiving the cam follower, and a drive mechanism effective to drive the cam plate to move relative to the housing. In the event that the cam follower is located in the working region of the cam slot, movement of the cam member in one direction urges the backplane structure towards the closed position and movement in the opposite direction urges the backplane structure away from the closed position.Type: GrantFiled: June 25, 2004Date of Patent: February 14, 2006Assignee: Credence Systems CorporationInventor: Wayne H. Miller