Patents Assigned to Cree, Inc.
  • Patent number: 11069635
    Abstract: A multi-cell transistor includes a semiconductor structure, a plurality of unit cell transistors that are electrically connected in parallel, each unit cell transistor extending in a first direction in the semiconductor structure, wherein the unit cell transistors are spaced apart from each other along a second direction, and an isolation structure that is positioned between a first group of the unit cell transistors and a second group of the unit cell transistors and that extends above the semiconductor structure.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: July 20, 2021
    Assignee: Cree, Inc.
    Inventors: Frank Trang, Qianli Mu, Haedong Jang, Zulhazmi Mokhti
  • Patent number: 11057033
    Abstract: A power module includes a plurality of power semiconductor devices. The plurality of power semiconductor devices includes an insulated gate bipolar transistor (IGBT) and a metal-oxide-semiconductor field-effect transistor (MOSFET) coupled in parallel between a first power switching terminal and a second power switching terminal. The IGBT and the MOSFET are silicon carbide devices. By providing the IGBT and the MOSFET together, a tradeoff between forward conduction current and reverse conduction current of the power module, the efficiency, and the specific current rating of the power module may be improved. Further, providing the IGBT and the MOSFET as silicon carbide devices may significantly improve the performance of the power module.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: July 6, 2021
    Assignee: Cree, Inc.
    Inventors: Edward Robert Van Brunt, Adam Barkley, Sei-Hyung Ryu, Zachary Cole, Kraig J. Olejniczak
  • Patent number: 11034056
    Abstract: Silicon carbide (SiC) wafers and related methods are disclosed that include intentional or imposed wafer shapes that are configured to reduce manufacturing problems associated with deformation, bowing, or sagging of such wafers due to gravitational forces or from preexisting crystal stress. Intentional or imposed wafer shapes may comprise SiC wafers with a relaxed positive bow from silicon faces thereof. In this manner, effects associated with deformation, bowing, or sagging for SiC wafers, and in particular for large area SiC wafers, may be reduced. Related methods for providing SiC wafers with relaxed positive bow are disclosed that provide reduced kerf losses of bulk crystalline material. Such methods may include laser-assisted separation of SiC wafers from bulk crystalline material.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: June 15, 2021
    Assignee: Cree, Inc.
    Inventors: Simon Bubel, Matthew Donofrio, John Edmond, Ian Currier
  • Patent number: 11031913
    Abstract: In integrating RF power amplifier circuits on a package, at least one bias voltage is coupled to at least one amplifier circuit on the package via two or more pins/connectors. In particular, at least one of a gate and drain bias voltage is coupled to one or more amplifier circuits via at least two pins/connectors. In some embodiments, the two or more bias voltage pins/connectors are connected together on the package, placing the pins/connectors in parallel, which reduces an inductance associated with the pins/connectors. In some embodiments, at least of the two pins/connectors connected to the same bias voltage are disposed on either side of an RF signal pin/conductor, simplifying the routing of signals on the package, affording greater flexibility of placement and routing on the package.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: June 8, 2021
    Assignee: Cree, Inc.
    Inventors: Madhu Chidurala, Marvin Marbell, Simon Ward
  • Patent number: 11024731
    Abstract: A power module is disclosed that includes a housing with an interior chamber wherein multiple switch modules are mounted within the interior chamber. The switch modules comprise multiple transistors and diodes that are interconnected to facilitate switching power to a load. In one embodiment, at least one of the switch modules supports a current density of at least 10 amperes per cm2.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: June 1, 2021
    Assignee: Cree, Inc.
    Inventors: Jason Patrick Henning, Qingchun Zhang, Sei-Hyung Ryu, Anant Kumar Agarwal, John Williams Palmour, Scott Allen
  • Patent number: 11024501
    Abstract: A method for removing a portion of a crystalline material (e.g., SiC) substrate includes joining a surface of the substrate to a rigid carrier (e.g., >800 ?m thick), with a subsurface laser damage region provided within the substrate at a depth relative to the surface. Adhesive material having a glass transition temperature above 25° C. may bond the substrate to the carrier. The crystalline material is fractured along the subsurface laser damage region to produce a bonded assembly including the carrier and a portion of the crystalline material. Fracturing of the crystalline material may be promoted by (i) application of a mechanical force proximate to at least one carrier edge to impart a bending moment in the carrier; (ii) cooling the carrier when the carrier has a greater coefficient of thermal expansion than the crystalline material; and/or (iii) applying ultrasonic energy to the crystalline material.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: June 1, 2021
    Assignee: CREE, INC.
    Inventors: Matthew Donofrio, John Edmond, Hua-Shuang Kong, Elif Balkas
  • Patent number: 11018631
    Abstract: Monolithic microwave integrated circuits are provided that include a substrate, a transmit/receive selection device that is formed on the substrate, a high power amplifier formed on the substrate and coupled to a first RF port of the transmit/receive selection device, a low noise amplifier formed on the substrate and coupled to a second RF port of the transmit/receive selection device and a protection circuit that is coupled to a first control port of the transmit/receive selection device.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: May 25, 2021
    Assignee: Cree, Inc.
    Inventor: Thomas J. Smith, Jr.
  • Patent number: 11004808
    Abstract: A multi-die package includes a thermally conductive flange, a first semiconductor die made of a first semiconductor material attached to the thermally conductive flange via a first die attach material, a second semiconductor die attached to the same thermally conductive flange as the first semiconductor die via a second die attach material, and leads attached to the thermally conductive flange or to an insulating member secured to the flange. The leads are configured to provide external electrical access to the first and second semiconductor dies. The second semiconductor die is made of a second semiconductor material different than the first semiconductor material. Additional multi-die package embodiments are described.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: May 11, 2021
    Assignee: CREE, INC.
    Inventors: Xikun Zhang, Dejiang Chang, Bill Agar, Michael Lefevre, Alexander Komposch
  • Patent number: 10998418
    Abstract: Power semiconductor devices include multi-layer inter-metal dielectric patterns that include at least one reflowed dielectric material pattern and at least one non-reflowable dielectric material pattern. In other embodiments, power semiconductor devices include reflowed inter-metal dielectric patterns that are formed using sacrificial structures such as dams to limit the lateral spread of the reflowable dielectric material of the inter-metal dielectric pattern during the reflow process. The inter-metal dielectric patterns may have improved shapes and performance.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: May 4, 2021
    Assignee: CREE, INC.
    Inventors: Edward R. Van Brunt, Daniel J. Lichtenwalner, Shadi Sabri
  • Patent number: 10991861
    Abstract: Flip chip LEDs incorporate multi-layer reflectors and light transmissive substrates patterned along an internal surface adjacent to semiconductor layers. A multi-layer reflector may include a metal layer and a dielectric layer containing conductive vias. Portions of a multi-layer reflector may wrap around a LED mesa including an active region, while being covered with passivation material. A substrate patterned along an internal surface together with a multi-layer reflector enables reduction of optical losses. A light transmissive fillet material proximate to edge emitting surfaces of an emitter chip may enable adequate coverage with lumiphoric material. An emitter chip may be elevated with increased thickness of solder material and/or contacts, and may reduce luminous flux loss when reflective materials are present on a submount.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: April 27, 2021
    Assignee: Cree, Inc.
    Inventors: Michael John Bergmann, Matthew Donofrio, Peter Scott Andrews, Colin Blakely, Troy Gould, Jack Vu
  • Patent number: 10978583
    Abstract: A semiconductor device includes a plurality of unit cell transistors on a common semiconductor structure, the unit cell transistors electrically connected in parallel, and each unit cell transistor including a respective gate finger. Respective threshold voltages of first and second of the unit cell transistors differ by at least 0.1 volts and/or threshold voltages of first and second segments of a third of the unit cell transistors differ by at least 0.1 volts.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: April 13, 2021
    Assignee: Cree, Inc.
    Inventors: Yueying Liu, Saptharishi Sriram, Scott Sheppard, Jennifer Gao
  • Patent number: 10971612
    Abstract: A power amplifier comprising a GaN-based high electron mobility transistor (HEMT) device, wherein a power added efficiency (PAE) of the power amplifier is greater than 32% at P1DB during operation of the power amplifier between 26.5 GHz and 30.5 GHz.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: April 6, 2021
    Assignee: Cree, Inc.
    Inventors: Kyle Bothe, Evan Jones, Dan Namishia, Chris Hardiman, Fabian Radulescu, Terry Alcorn, Scott Sheppard, Bruce Schmukler
  • Patent number: 10964858
    Abstract: Light emitting diodes, components, and related methods, with improved performance over existing light emitting diodes. In some embodiments, light emitter devices included herein include a submount, a light emitter, a light affecting material, and a wavelength conversion component. Wavelength conversion components provided herein include a transparent substrate having an upper surface and a lower surface, and a phosphor compound disposed on the upper surface or lower surface, wherein the wavelength conversion component is configured to alter a wavelength of a light emitted from a light source when positioned proximate to the light source.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: March 30, 2021
    Assignee: Cree, Inc.
    Inventors: Peter Scott Andrews, Jesse Colin Reiherzer, Amber C. Abare
  • Patent number: 10962199
    Abstract: Solid state lighting components are provided with improved color rendering, improved color uniformity, and improved directional lighting, and that are suitable for use in high output lighting applications and can be used in place of CDMH bulb lighting. Exemplary solid state lighting components include a substrate comprising a light emitter surface and or more light emitters disposed on and/or over the light emitter surface. Exemplary components include a light directing optic and/or a diffusing optic for mixing light. The light directing optic may be disposed at least partially around a perimeter of the light emitter surface. The diffusing optic may be disposed between portions of the light directing optic and spaced apart from the light emitter surface.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: March 30, 2021
    Assignee: Cree, Inc.
    Inventors: Florin A. Tudorica, Christopher P. Hussell, John Wesley Durkee, Peter Scott Andrews, Mark Cash, David Randolph
  • Patent number: 10964866
    Abstract: An adaptive electrical routing system for constructing an LED device. The system takes into account placement errors and tolerance regions for connection of one or more LEDs on a substrate. An optical device captures an image (e.g., comprising positional data of components of the LED device) of the LED device showing the actual placement of LEDs on the substrate and transfers the image to an analysis program. A customized pattern (e.g., a customized electrical routing pattern) can be created in one of several possible ways.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: March 30, 2021
    Assignee: Cree, Inc.
    Inventor: Christopher P. Hussell
  • Patent number: 10957830
    Abstract: Monolithic LED chips are disclosed comprising a plurality of active regions on a submount, wherein the submount comprises integral electrically conductive interconnect elements in electrical contact with the active regions and electrically connecting at least some of the active regions in series. The submount also comprises an integral insulator element electrically insulating at least some of the interconnect elements and active regions from other elements of the submount. The active regions are mounted in close proximity to one another to minimize the visibility of the space during operation. The LED chips can also comprise layers structures and compositions that allow improved reliability under high current operation.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: March 23, 2021
    Assignee: Cree, Inc.
    Inventors: Bradley E Williams, Kevin W Haberern, Bennett D Langsdorf, Manuel L Breva
  • Patent number: 10957736
    Abstract: Light emitting diode (LED) components include a submount, at least one or more LED chip wirebonded on a first surface of the submount to electrical traces at the edges of the submount, and a molded encapsulant which is devoid of a curved lens or hemispherical lens and can have outer or lateral walls co-planar with exterior walls of the submount. An LED component can have a viewing angle that is greater than 125°. A method of providing an LED component includes providing a substantially flat submount, attaching one or more LED chip over a first surface of the submount, dispensing an encapsulant over the first surface of the submount over the LED chips, applying a press over the encapsulant to apply a heat and/or pressure to the encapsulant, and molding the encapsulant over the first surface of the submount.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: March 23, 2021
    Assignee: Cree, Inc.
    Inventors: Aaron J. Francis, Jasper Sicat Cabalu, Colin Kelly Blakely
  • Patent number: 10950769
    Abstract: A Light Emitting Diode (LED) component includes a lead frame and an LED that is electrically connected to the lead frame without wire bonds, using a solder layer. The lead frame includes a metal anode pad, a metal cathode pad and a plastic cup. The LED die includes LED die anode and cathode contacts with a solder layer on them. The metal anode pad, metal cathode pad, plastic cup and/or the solder layer are configured to facilitate the direct die attach of the LED die to the lead frame without wire bonds. Related fabrication methods are also described.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: March 16, 2021
    Assignee: Cree, Inc.
    Inventors: Michael John Bergmann, Colin Kelly Blakely, Arthur Fong-Yuen Pun, Jesse Colin Reiherzer
  • Patent number: 10950719
    Abstract: A vertical field-effect transistor (FET) device includes a monolithically integrated bypass diode connected between a source contact and a drain contact of the vertical FET device. According to one embodiment, the vertical FET device includes a pair of junction implants separated by a junction field-effect transistor (JFET) region. At least one of the junction implants of the vertical FET device includes a deep well region that is shared with the integrated bypass diode, such that the shared deep well region functions as both a source junction in the vertical FET device and a junction barrier region in the integrated bypass diode. The vertical FET device and the integrated bypass diode may include a substrate, a drift layer over the substrate, and a spreading layer over the drift layer, such that the junction implants of the vertical FET device are formed in the spreading layer.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: March 16, 2021
    Assignee: Cree, Inc.
    Inventors: Vipindas Pala, Lin Cheng, Anant Kumar Agarwal, John Williams Palmour, Edward Robert Van Brunt
  • Patent number: 10944031
    Abstract: A solid state lighting package is provided. The package comprising at least one LED element positioned on a top surface of a substrate and a conformal reflective layer of inorganic particles, whereby at least of portion of the light emitted by the LED element is reflected by the conformal reflective layer. A method of manufacturing a solid state lighting package comprising the distribution of inorganic particles, and a method of increasing the luminous flux thereof, is also provided.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: March 9, 2021
    Assignee: Cree, Inc.
    Inventor: Peter Andrews