Patents Assigned to Cree, Inc.
  • Patent number: 11257940
    Abstract: A High Mobility Electron Transistor (HEMT) and a capacitor co-formed on an integrated circuit (IC) share at least one structural feature, thereby tightly integrating the two components. In one embodiment, the shared feature may be a 2DEG channel of the HEMT, which also functions in lieu of a base metal layer of a conventional capacitor. In another embodiment, a dialectic layer of the capacitor may be formed in a passivation step of forming the HEMT. In another embodiment, a metal contact of the HEMT (e.g., source, gate, or drain contact) comprises a metal layer or contact of the capacitor. In these embodiments, one or more processing steps required to form a conventional capacitor are obviated by exploiting one or more processing steps already performed in fabrication of the HEMT.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: February 22, 2022
    Assignee: Cree, Inc.
    Inventors: Evan Jones, Jeremy Fisher
  • Patent number: 11228287
    Abstract: An electronic package houses one or more RF amplifier circuits. At least one of an input or output impedance matching network integrated on the package and electrically coupled to the gate or drain bias voltage connection, respectively, of an amplifier circuit, includes a multi-stage decoupling network. Each multi-stage decoupling network includes two or more decoupling stages. Each decoupling stage of the multi-stage decoupling network includes a resistance, inductance, and capacitance, and is configured to reduce impedance seen by the amplifier circuit at a different frequency below an operating band of the amplifier circuit. Bias voltage connections to the impedance matching circuits may be shared, and may be connected anywhere along the multi-stage decoupling network.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: January 18, 2022
    Assignee: Cree, Inc.
    Inventors: Madhu Chidurala, Marvin Marbell, Niklas Thulin
  • Patent number: 11201591
    Abstract: In an asymmetric Doherty amplifier circuit, one or more shunt reactive components are added to at least one side of an impedance inverter connecting the amplifier outputs, to reduce a capacitance imbalance between the two amplifiers caused by their different parasitic capacitances. This enables the (adjusted) parasitic capacitances to be incorporated into a quarter-wavelength transmission line, having a 90-degree phase shift, for the impedance inverter. In one embodiment, a shunt inductance is connected between the impedance inverter, on the side of the larger amplifier, and RF signal ground. The inductance is sized to resonate away substantially the excess parasitic capacitance of the larger amplifier. In another embodiment, a shunt capacitor is connected on the side of the smaller amplifier, thus raising its total capacitance to substantially equal the parasitic capacitance of the larger amplifier.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: December 14, 2021
    Assignee: Cree, Inc.
    Inventors: Haedong Jang, Sonoko Aristud, Marvin Marbell, Madhu Chidurala
  • Patent number: 11184001
    Abstract: Power switching devices include a semiconductor layer structure that has an active region and an inactive region. The active region includes a plurality of unit cells and the inactive region includes a field insulating layer on the semiconductor layer structure and a gate bond pad on the field insulating layer opposite the semiconductor layer structure. A gate insulating pattern is provided on the semiconductor layer structure between the active region and the field insulating layer, and at least one source/drain contact is provided on the semiconductor layer structure between the gate insulating pattern and the field insulating layer.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: November 23, 2021
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Adam Barkley, Sei-Hyung Ryu, Brett Hull
  • Patent number: 11175333
    Abstract: A process and system for testing includes: arranging devices in a temperature-controlled environment; applying a negative gate bias voltage (Vgs) to the devices; applying a drain voltage (Vds) to the devices; measuring currents and/or voltages of the devices to generate device test data; determining a failure of one or more of the devices based on the device test data generated from the device currents and/or the voltages to generate failure data; and outputting the failure data for the of devices.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: November 16, 2021
    Assignee: CREE, INC.
    Inventors: Daniel Jenner Lichtenwalner, Satyaki Ganguly
  • Patent number: 11171229
    Abstract: The present disclosure relates to a power module that has a housing with an interior chamber and a plurality of switch modules interconnected to facilitate switching power to a load. Each of the plurality of switch modules comprises at least one transistor and at least one diode mounted within the interior chamber and both the at least one transistor and the at least one diode are majority carrier devices, are formed of a wide bandgap material system, or both. The switching modules may be arranged in virtually any fashion depending on the application. For example, the switching modules may be arranged in a six-pack, full H-bridge, half H-bridge, single switch or the like.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: November 9, 2021
    Assignee: Cree, Inc.
    Inventors: Mrinal K. Das, Robert J. Callanan, Henry Lin, John Williams Palmour
  • Patent number: 11164967
    Abstract: A power MOSFET includes a silicon carbide drift region having a first conductivity type, first and second well regions located in upper portions of the silicon carbide drift region that are doped with second conductivity dopants, and a channel region in a side portion of the first well region, an upper portion of the channel region having the first conductivity type, wherein a depth of the first well region is at least 1.5 microns and the depth of the first well region exceeds a distance between the first and second well regions.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: November 2, 2021
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Alexander V. Suvorov
  • Patent number: 11164813
    Abstract: A transistor semiconductor die includes a drift layer, a first dielectric layer, a first metallization layer, a second dielectric layer, a second metallization layer, a first plurality of electrodes, and a second plurality of electrodes. The first dielectric layer is over the drift layer. The first metallization layer is over the first dielectric layer such that at least a portion of the first metallization layer provides a first contact pad. The second dielectric layer is over the first metallization layer. The second metallization layer is over the second dielectric layer such that at least a portion of the second metallization layer provides a second contact pad and the second metallization layer at least partially overlaps the first metallization layer. The transistor semiconductor die is configured to selectively conduct current between the first contact pad and a third contact pad based on signals provided at the second contact pad.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: November 2, 2021
    Assignee: Cree, Inc.
    Inventors: Daniel Jenner Lichtenwalner, Edward Robert Van Brunt
  • Patent number: 11152325
    Abstract: A semiconductor device package includes a package substrate having a die attach region, a silicon carbide (SiC) substrate having a first surface including a semiconductor device layer thereon and a second surface that is opposite the first surface, and a die attach metal stack. The die attach metal stack includes a sputtered die attach material layer that attaches the second surface of the SiC substrate to the die attach region of the package substrate, where the sputtered die attach material layer comprises a void percent of about 15% or less. The sputtered die attach material layer may be formed using a sputter gas including at least one of krypton (Kr), xenon (Xe), or radon (Rn). The die attach metal stack may further include a metal interlayer that prevent contacts with a first barrier metal layer during a phase transition of the die attach material layer.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: October 19, 2021
    Assignee: Cree, Inc.
    Inventors: Alexander Komposch, Kevin Schneider, Scott Sheppard
  • Patent number: 11139810
    Abstract: Support circuitry for a power transistor includes a feedback switching element and switching control circuitry. The feedback switching element is coupled between a Kelvin connection node and a second power switching node. The switching control circuitry is configured to cause the feedback switching element to couple the Kelvin connection node to the second power switching node after the power transistor is switched from a blocking mode of operation to a conduction mode of operation and cause the feedback switching element to isolate the Kelvin connection node from the second power switching node before the power transistor is switched from the conduction mode of operation to the blocking mode of operation.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: October 5, 2021
    Assignee: Cree, Inc.
    Inventors: Cam Pham, Alejandro Esquivel Rodriguez
  • Patent number: 11135669
    Abstract: A process for manufacturing an electronic component having attaches includes providing a first component having a first attach, forming trenches on a portion of the first attach with a laser to form a solder stop, and providing a second component comprising a second attach. The process further includes providing solder between the first attach and the second attach to form a connection between the first component and the second component, where the trenches contain the solder to a usable area. A device produced by the process is disclosed as well.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: October 5, 2021
    Assignee: CREE, INC.
    Inventors: Jennifer Stabach, Brice McPherson, Chad B. O'Neal
  • Patent number: 11114396
    Abstract: In a transistor formed on a semiconductor die mounted on a substrate, where the transistor output is connected to a circuit on the substrate, a bond pad electrically connected to a transistor drain finger manifold extends less than the full length of the manifold. By controlling the length of the bond pad, the parasitic capacitance it contributes may be controlled. In applications such as a Doherty amplifier, this parasitic capacitance forms part of the quarter-wave transmission line of an impedance inverter, and hence directly impacts amplifier performance. In particular, by reducing the parasitic capacitance contribution from transistor output bond pads, the bandwidth of a Doherty amplifier circuit may be improved. At GHz frequencies and with state of the art transistor device feature sizes, concerns about phase mismatch between drain finger outputs are largely moot.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: September 7, 2021
    Assignee: Cree, Inc.
    Inventors: Lei Zhao, Mario Bokatius
  • Patent number: 11114988
    Abstract: In a Doherty amplifier, outputs of first (main) and second (peak) transistors are connected by a combined impedance inverter and harmonic termination circuit. The harmonic termination circuit incorporates a predetermined part of the impedance inverter, and provides a harmonic load impedance at a targeted harmonic frequency (e.g., the second harmonic). Control of the amplitude and phase of the harmonic load impedance facilitates shaping of the drain current and voltage waveforms to maximize gain and efficiency, while maintaining a good load modulation at a fundamental frequency. Particularly for Group III nitride semiconductors, such as GaN, both harmonic control and output impedance matching circuits may be eliminated from the outputs of each transistor. The combined impedance inverter and harmonic termination circuit reduces the amplifier circuit footprint, for high integration and low power consumption.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: September 7, 2021
    Assignee: Cree, Inc.
    Inventors: Jangheon Kim, Sonoko Aristud, Michael E. Watts, Mario Bokatius
  • Patent number: 11075295
    Abstract: A metal-oxide-semiconductor field-effect transistor includes a wide bandgap substrate, a wide bandgap drift layer over the substrate, a number of junction implants in the drift layer, and a JFET region between the junction implants. The JFET region is defined by a JFET gap, which is the distance between adjacent ones of the junction implants. The JFET gap is not uniform throughout the MOSFET device. The JFET region is separated into a first JFET sub-region and a second JFET sub-region, such that a doping concentration in the first JFET sub-region is different from a doping concentration in the second JFET sub-region.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: July 27, 2021
    Assignee: Cree, Inc.
    Inventor: Sei-Hyung Ryu
  • Patent number: 11075264
    Abstract: Semiconductor devices include a silicon carbide drift region having an upper portion and a lower portion. A first contact is on the upper portion of the drift region and a second contact is on the lower portion of the drift region. The drift region includes a superjunction structure that includes a p-n junction that is formed at an angle of between 10° and 30° from a plane that is normal to a top surface of the drift region. The p-n junction extends within +/?1.5° of a crystallographic axis of the silicon carbide material forming the drift region.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: July 27, 2021
    Assignee: Cree, Inc.
    Inventors: Edward Robert Van Brunt, Alexander V. Suvorov, Vipindas Pala, Daniel J. Lichtenwalner, Qingchun Zhang
  • Patent number: 11075271
    Abstract: A transistor includes a semiconductor layer structure, a source electrode and a drain electrode on the semiconductor layer structure, a gate on a surface of the semiconductor layer structure between the source electrode and the drain electrode, and a field plate. The field plate includes a first portion adjacent the gate and a second portion adjacent the source or drain electrode. The second portion of the field plate is farther from the surface of the semiconductor layer structure than the first portion of the field plate, and is closer to the surface of the semiconductor layer structure than an extended portion of the gate. Related devices and fabrication methods are also discussed.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: July 27, 2021
    Assignee: Cree, Inc.
    Inventors: Evan Jones, Terry Alcorn, Jia Guo, Fabian Radulescu, Scott Sheppard
  • Patent number: 11069635
    Abstract: A multi-cell transistor includes a semiconductor structure, a plurality of unit cell transistors that are electrically connected in parallel, each unit cell transistor extending in a first direction in the semiconductor structure, wherein the unit cell transistors are spaced apart from each other along a second direction, and an isolation structure that is positioned between a first group of the unit cell transistors and a second group of the unit cell transistors and that extends above the semiconductor structure.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: July 20, 2021
    Assignee: Cree, Inc.
    Inventors: Frank Trang, Qianli Mu, Haedong Jang, Zulhazmi Mokhti
  • Patent number: 11057033
    Abstract: A power module includes a plurality of power semiconductor devices. The plurality of power semiconductor devices includes an insulated gate bipolar transistor (IGBT) and a metal-oxide-semiconductor field-effect transistor (MOSFET) coupled in parallel between a first power switching terminal and a second power switching terminal. The IGBT and the MOSFET are silicon carbide devices. By providing the IGBT and the MOSFET together, a tradeoff between forward conduction current and reverse conduction current of the power module, the efficiency, and the specific current rating of the power module may be improved. Further, providing the IGBT and the MOSFET as silicon carbide devices may significantly improve the performance of the power module.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: July 6, 2021
    Assignee: Cree, Inc.
    Inventors: Edward Robert Van Brunt, Adam Barkley, Sei-Hyung Ryu, Zachary Cole, Kraig J. Olejniczak
  • Patent number: 11034056
    Abstract: Silicon carbide (SiC) wafers and related methods are disclosed that include intentional or imposed wafer shapes that are configured to reduce manufacturing problems associated with deformation, bowing, or sagging of such wafers due to gravitational forces or from preexisting crystal stress. Intentional or imposed wafer shapes may comprise SiC wafers with a relaxed positive bow from silicon faces thereof. In this manner, effects associated with deformation, bowing, or sagging for SiC wafers, and in particular for large area SiC wafers, may be reduced. Related methods for providing SiC wafers with relaxed positive bow are disclosed that provide reduced kerf losses of bulk crystalline material. Such methods may include laser-assisted separation of SiC wafers from bulk crystalline material.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: June 15, 2021
    Assignee: Cree, Inc.
    Inventors: Simon Bubel, Matthew Donofrio, John Edmond, Ian Currier
  • Patent number: 11031913
    Abstract: In integrating RF power amplifier circuits on a package, at least one bias voltage is coupled to at least one amplifier circuit on the package via two or more pins/connectors. In particular, at least one of a gate and drain bias voltage is coupled to one or more amplifier circuits via at least two pins/connectors. In some embodiments, the two or more bias voltage pins/connectors are connected together on the package, placing the pins/connectors in parallel, which reduces an inductance associated with the pins/connectors. In some embodiments, at least of the two pins/connectors connected to the same bias voltage are disposed on either side of an RF signal pin/conductor, simplifying the routing of signals on the package, affording greater flexibility of placement and routing on the package.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: June 8, 2021
    Assignee: Cree, Inc.
    Inventors: Madhu Chidurala, Marvin Marbell, Simon Ward