Abstract: Providing for improved cell longevity for two-terminal memory devices is described herein. By way of example, wear leveling and management of array operations is provided to reduce an average number of set or reset cycles employed for programming new data to a two-terminal memory device. Reduction in set and reset cycles can facilitate reduced wear over time, increasing longevity of the memory device and enabling larger numbers of lifetime array operations. Wear leveling can comprise comparing existing data stored within a target set of memory cells, to new data to be written to the target cells, and changing only cells having different values between the existing and new data. In some examples, new data can be inverted to reduce a number of program or erase pulses required to program the new data over the existing data, among other examples of disclosed wear leveling.

Abstract: A semiconductor device includes first electrodes disposed upon a substrate, wherein each first electrode comprises a metal containing material, switching devices disposed overlying the first electrodes, wherein each switching device comprises a first switching material, a second switching material, and an active metal, wherein the first switching material is disposed overlying and contacting the first electrodes, wherein the second switching material is disposed overlying and contacting the first switching material, wherein the active metal is disposed overlying and contacting the second switching material, wherein the first switching material is characterized by a first switching voltage, wherein the second switching material is characterized by a second switching voltage greater than the first switching voltage; and second electrodes disposed above the switching devices, comprising the metal material, and wherein each of the second electrodes is electrically coupled to the active metal material of the switc

Abstract: Providing for a high performance and efficiency NAND architecture is described herein. By way of example, a NAND array is disclosed comprising memory cells having a 1 transistor-1 two-terminal memory device (IT-1D) arrangement. Memory cells of the NAND array can be arranged electrically in serial with respect to each other, from source to drain. Moreover, respective memory cells comprise a transistor component connected in parallel to a two-terminal memory device. In some embodiments, a resistance of the activated transistor component is selected to be substantially less than that of the two-terminal memory device, and the resistance of the deactivated transistor component is selected to be substantially higher than the two-terminal memory device. Accordingly, by activating or deactivating the transistor component, a signal applied to the memory cell can be shorted past the two-terminal memory device, or directed through the two-terminal memory device, respectively.

Abstract: Provision of fabrication, construction, and/or assembly of a two-terminal memory device is described herein. The two-terminal memory device can include an active region with a silicon bearing layer, an interface layer, and an active metal layer. The interface layer can created comprising a non-stoichiometric sub-oxide that can be a combination of multiple silicon and/or silicon oxide layers with an aggregate chemical formula of SiOX, where X can be a non-integer greater than zero and less than 2. The sub-oxide can be created in a variety of ways, including various techniques related to growing the sub-oxide, depositing the sub-oxide, or transforming an extant film into the sub-oxide.

Abstract: Providing a RRAM based memory storage device that has a NAND memory type architecture with a configurable page size. In an embodiment, two memory registers can be used to access and transfer data stored in the storage device to a host. A memory controller on the storage device can determine a page size of the host, and alternately transfer data from the first register and then the second register until an amount of data transferred equals the page size of the host. The memory controller can send the data to the host as if the data belonged to one page transfer. In this way, the memory controller creates a virtualized page size based on the requirements of the host.

Abstract: A method includes patterning a layered structure comprising a monolithic stack including a bottom electrode surrounded by a dielectric material, a switching material, a barrier material, a dielectric hardmask, and a patterned photoresist formed above and adjacent to a portion of the dielectric hardmask. The patterning includes patterning the dielectric hardmask using a first etchant and employing the patterned photoresist as a mask, patterning the barrier material using a second etchant and employing a portion of the dielectric hardmask remaining after the patterning the dielectric hardmask as a mask, and patterning the switching material using ion milling or etching and employing the portion of the dielectric hardmask remaining after the patterning the barrier material as a mask.

Abstract: A resistive switching device. The device includes a first electrode comprising a first metal material overlying the first dielectric material and a switching material comprising an amorphous silicon material. The device includes a second electrode comprising at least a second metal material. In a specific embodiment, the device includes a buffer material disposed between the first electrode and the switching material. The buffer material provides a blocking region between the switching material and the first electrode so that the blocking region is substantially free from metal particles from the second metal material when a first voltage is applied to the second electrode.

Abstract: A memory device comprising a doped conductive polycrystalline layer having an electrically resistive portion, is described herein. By way of example, ion implantation to a subset of the conductive polycrystalline layer can degrade and modify the polycrystalline layer, forming the electrically resistive portion. The electrically resistive portion can include resistive switching properties facilitating digital information storage. Parametric control of the ion implantation can facilitate control over corresponding resistive switching properties of the resistive portion. For example, a projected range or depth of the ion implantation can be controlled, allowing for preferential placement of atoms in the resistive portion, and fine-tuning of a forming voltage of the memory device. As another example, dose and number of atoms implanted, type of atoms or ions that are implanted, the conductive polycrystalline material used, and so forth, can facilitate control over switching characteristics of the memory device.

Abstract: Providing for a non-volatile memory architecture having write and overwrite capabilities providing low write amplification to a storage system is described herein. By way of example, a memory array is disclosed comprising blocks and sub-blocks of two-terminal memory cells. The two-terminal memory cells can be directly overwritten in some embodiments, facilitating a write amplification value as low as one. Furthermore, the memory array can have an input-output multiplexer configuration, reducing sneak path currents of the memory architecture during memory operations.

Abstract: A non-volatile memory device includes a first dielectric on a substrate, a first electrode disposed on the first dielectric, a second dielectric material disposed next to the first electrode, a patterned material disposed upon the second dielectric material and in contact with part of the first electrode, a third dielectric material disposed next to the patterned material and in contact with another part of the first electrode, wherein the patterned material and the third dielectric material contact at an interface region, wherein the interface region is characterized by a plurality of defects, a second electrode disposed on the patterned material, on the third dielectric, and on the interface region, wherein the second electrode comprises metal particles that are configured to be diffused within the interface region upon application of a bias voltage, and wherein metal particles are disposed within the plurality of defects in the interface region.

Abstract: Providing for three-dimensional memory cells having enhanced electric field characteristics and/or memory cells located at broken interconnects is described herein. By way of example, a two-terminal memory cell can be constructed from a layered stack of materials, where respective layers are arranged along a direction that forms a non-zero angle to a normal direction of a substrate surface upon which the layered stack of materials is constructed. In some aspects, the direction can be orthogonal to or substantially orthogonal to the normal direction. In other aspects, the direction can be less than orthogonal to the normal direction. Where an internal angle of the memory cell forms a non-orthogonal angle, an enhanced electric field or current density can result, providing improved switching times and memory performance.

Abstract: Providing for three-dimensional memory cells having enhanced electric field characteristics and/or memory cells located at broken interconnects is described herein. By way of example, a two-terminal memory cell can be constructed from a layered stack of materials, where respective layers are arranged along a direction that forms a non-zero angle to a normal direction of a substrate surface upon which the layered stack of materials is constructed. In some aspects, the direction can be orthogonal to or substantially orthogonal to the normal direction. In other aspects, the direction can be less than orthogonal to the normal direction. Where an internal angle of the memory cell forms a non-orthogonal angle, an enhanced electric field or current density can result, providing improved switching times and memory performance.

Abstract: A solid state memory comprises a top electrode, a bottom electrode and an insulating switching medium that is disposed at a thickness based on a predetermined function. The insulating switching medium generates a conduction path in response to an electric signal applied to the device. The thickness of the insulating switching medium is a function of a filament width of the conduction path and operates to prevent rupture of a semi-stable region. The semi-stable region maintains filament structure over time and does not degrade into retention failure. The solid state memory can comprise one or more conducting layers that can operate to control the conductance at an on-state of the memory and offer oxygen vacancies or metal ions to the switching medium. The function of the thickness of the insulating switching medium can vary depending upon the number of conduction layers disposed at the insulating switching medium.

Abstract: A switching device includes a substrate; a first electrode formed over the substrate; a second electrode formed over the first electrode; a switching medium disposed between the first and second electrode; and a nonlinear element disposed between the first and second electrodes and electrically coupled in series to the first electrode and the switching medium. The nonlinear element is configured to change from a first resistance state to a second resistance state on application of a voltage greater than a threshold.

Abstract: Two-terminal memory can be configured as multi-level cell (MLC) memory in which a single memory cell can represent multiple bits of information. Unlike certain other memories that are subject to disturb errors, for the disclosed two-terminal memory, these multiple bits can store information that is included in the same logical page of memory, which can be advantageous. However, performing error-code correction (ECC) operations on multiple bits of data from the same MLC can result in additional stress on an ECC engine because if a MLC fails, all bits of that cell are likely to be bad. Splitting the multiple bits of a MLC in connection with encoding or decoding can average the errors from bad cells across multiple ECC codewords, thereby providing better coverage with the same ECC or reducing the overhead associated with ECC coverage.

Abstract: Provision of fabrication, construction, and/or assembly of a memory device including a two-terminal memory portion is described herein. The two-terminal memory device fabrication can provide enhanced capabilities in connection with precisely tuning on-state current over a greater possible range.

Abstract: Providing for a memory cell capable of forming a one time programmable, multi-level cell two-terminal memory cell or a rewritable, two terminal memory cell is described herein. In some embodiments, one time programmable, multi-level cell two-terminal memory cell can exhibit diode-like characteristics. In other embodiments, the memory cell can comprise a first electrode layer configured to generate ions in response to an electric field applied to the memory cell; a resistive ion migration layer at least in part permeable to migration of the ions within the resistive ion migration layer; a second electrode layer; and a substrate layer comprising a silicon wafer.

Abstract: A memory system including a memory device. The memory device includes a substrate. A memory array defines a plurality of pages, each page including a data area for storing data and a spare area for storing metadata. A compare circuit is configured to receive metadata retrieved from a plurality of pages sequentially and compare the retrieved metadata to a search pattern. The physical location of the page can be determined by finding the search pattern. The memory array and the compare circuit are formed in different layers of the substrate.

Abstract: A two-terminal memory array can be configured to address a single memory cell. A two-terminal memory array can further be configured to mitigate disturb errors associated with other types of memory (e.g., non-two-terminal memory such as NAND flash memory). Mitigation of disturb errors can allow re-writes and/or overwrites of data stored by the cells without a prior erase operation. In this regard, errors in the data read from a memory array can be corrected by error-correction code (ECC) and associated corrected data can be written back to the memory cells that store the portions of data determined by the ECC to be erroneous data and/or incorrect or bad data.

Abstract: Method for a memory including a first, second, third and fourth cells include applying a read, program, or erase voltage, the first and second cells coupled to a first top interconnect, the third and fourth cells coupled to a second top interconnect, the first and third cells coupled to a first bottom interconnect, the second and fourth cells are to a second bottom interconnect, each cell includes a switching material overlying a non-linear element (NLE), the resistive switching material is associated with a first conductive threshold voltage, the NLE is associated with a lower, second conductive threshold voltage, comprising applying the read voltage between the first top and the first bottom electrode to switch the NLE of the first cell to conductive, while the NLEs of the second, third, and the fourth cells remain non-conductive, and detecting a read current across the first cell in response to the read voltage.