Abstract: An analog-to-digital converter includes a two-bit delta-sigma modulator. The delta-sigma modulator is comprised of a first stage integrator (10) that feeds a noise shaping circuit (18). The output of the noise shaping circuit (18) is input to a two-threshold imbedded ADC (20) to provide the two-bit output. This output of the imbedded ADC (20) is input to a digital filter (22) to provide the filtered digital output, this filtering high-frequency noise. The output of the imbedded ADC (20) is also fed back through a three-level DAC (24) to a summing junction on the input of the integrator (10). The three-level DAC 24 has three states that are output with one state being a "do nothing" state. The thermal noise performance of the delta-sigma modulator as a function of the quantizer threshold voltages is first simulated and then the value of the quantizer thresholds selected to provide optimum signal-to-thermal noise performance.

Abstract: A low drift integrated circuit resistor structure has a forced high end and a forced low end. A sense high connection is located proximate to the force high connection, and a sense low connection is located proximate to the force low connection. The structure also has at least one internal sense connection. This structure can be used in an instrumentation amplifier that includes an operational amplifier which regulates the current between the force high connection and the force low connection in response, in part, to the current sensed in the internal sensing connection of the resistor structure. The sense high connection and the sense low connection form the outputs of the instrumentation amplifier.

Abstract: A digital-to-analog converter for operating in a low power condition includes a delta-sigma modulator (10) for converting an n-bit digital input signal to an m-bit digital output signal. The output signal is filtered with a switched-capacitor filter (12) and an active RC low-pass filter (18). A low power supply detect circuit receives two power supply input voltages, the low and the high power supplies, and outputs a control signal on a line (38) indicating a low power supply condition. The digital-to-analog converter includes an output stage (26) with the analog output thereof being connected to an analog output terminal (30). A switch (28) is provided for connecting the output stage to the analog output terminal (30) in normal operating mode. In a low power mode, the low power detect circuit (20) generates a control signal on line (38) in response to the power supply voltage falling below a predetermined threshold.

Abstract: A switched capacitor input circuit that reduces nonlinear input current due to input switch charge injection. The addition of a shunt capacitor with a series switch to signal ground at the input switch of a sampling network is used to sample and hold the input switch charge injection. This input switch charge injection can then be returned as input switch channel charge during the next sampling phase eliminating the need for the input signal to supply this charge.

Abstract: A ratiometric converter is provided that is comprised of a dual converter system utilizing a first converter (36) and a second converter (38). The second converter (38) is operable to receive the input voltage from a load cell (10) on sense lines (12) and (14) and compare them with an internal reference. Similarly, the first A/D converter (36) is operable to receive the reference voltage to the load cell (10) and compare it with the internal reference. The output of each of the converters (36) and (38) is then input to subtraction circuits (78) and (84), respectively, in the digital domain. In a calibration mode, switches (72) and (73) shorts the reference nodes in the load cell (10) together to determine the non-ratiometric offsets., These offsets are then stored in registers (80) and (86) for the reference voltage and the input voltage, respectively.

Abstract: An analog-to-digital converter includes a delta-sigma modulator (10), having the output thereof filtered by a digital filter section. The digital filter section includes a first fixed decimation filter (12) followed by a variable decimation filter section (14) and an output low-pass filter section (16), having a fixed decimation ratio. The fixed variable decimation filter section (14) includes a single FIR filter (24) that has data processed therethrough with different sampling rates. A recursive controller (26) receives an external configuration input to determine the number of passes through the filter (24) that are required to provide the desired decimation ratio.

Abstract: A clock multiplier/jitter attenuator circuit provides a stable clock which is a multiple frequency of the average frequency of an external digital data stream. The external data is written into successive storage cells of a FIFO at its own clock rate and read out of the FIFO at the rate of an internal clock signal which is formed by frequency dividing the stable clock. The relative locations of the cell being written into and the cell being read out of are determined at periodic time intervals, and these relative locations are used to adjust the frequency of an internal oscillator which generates the stable clock. The instantaneous jitter on the digital data stream is absorbed by the FIFO.

Abstract: A high speed feedback amplifier is frequency compensated utilizing circuitry that does not cause distortion in the amplifier nor does it limit the slew rate of the amplifier. In one embodiment compensation circuitry drives one side of the compensation capacitor forcing the signal voltage across the compensation capacitor to zero while still providing bandwidth compensation. Since no current gets driven into the capacitor, no distortion or slew limitations are created by the compensation. In a second embodiment the voltage across the compensation capacitor is allowed to change, however the signal current for the compensation capacitor is supplied by a linear charging circuit which removes this charging requirement from the amplifier. Therefore, as in the first embodiment, no distortion or slew limitation is created by the addition of the frequency compensation.

Abstract: An amplifier with controlled output impedance has a first output connected to the inverting input of the amplifier, and a second output, which forms the output of the amplifier, connected through a feedback conductance to the inverting input of the amplifier. A input conductance is connected from the inverting input to ground, and the input signal is connected to the positive input of the amplifier. The first and second outputs are provided by first and second current output stages. The currents provided by the first and second output stages are proportional to each other by a predetermined ratio. By proper selection of this predetermined ratio and the feedback and input conductances the desired output impedance and overall gain of the amplifier into a given load can be achieved.

Abstract: A wide bandwidth transconductance amplifier utilizing internal feedback is stabilized over a wide range of output currents. A compensation driver circuit senses the output current in the amplifier and feeds it back through a compensation capacitor. This keeps the bandwidth of the amplifier constant and optimally stabilized over a 16 to 1 range in output current. This compensation scheme eliminates compensation compromises that can limit the useful dynamic range of transconductnce amplifiers while offering a wide bandwidth low distortion transconductance with high output impedance over frequency.

Abstract: An oversampling analog-to-digital modulator includes an analog loop filter which has a first integrator stage which operates as a continuous time integrator. the second, third, and fourth integrator stages are discrete time or sampling integrators. The continuous time first integrator provides the required thermal noise characteristics of the loop filter while the discrete time integrator stages provide loop stability and transfer characteristics which are advantageous to the overall operation of the analog-to-digital modulator.

Abstract: An oversampling analog-to-digital modulator includes an analog loop filter which has a first integrator stage which is a single-ended integrator. The second, third, and fourth integrator stages are fully-differential integrators. The first integrator provides the required thermal noise characteristics of the loop filter with only one feedback capacitor which is external to the integrated circuit chip, while the fully-differential integrator stages provide improved suppression of charge injection transients.

Abstract: A phase equalization system for a digital-to-analog converter (DAC) includes a digital portion (10) having an interpolation section (14) for receiving a digital input and increasing the sampling frequency thereof for input to a delta-sigma modulator (16). A summing junction (24) is disposed between the interpolation circuit (14) and the delta-sigma modudlator (16) to allow an offset voltage to be summed therewith. This provides for D.C. offset, this offset being controlled by a calibration control (40). The output of the digital section (10) is input in an analog section (12), which has a one-bit DAC 21) that is input to an analog filter (22) for converting and filtering the one-bit digital stream output by the delta-sigma modulator (16). The interpolation circuit (14) includes a three stage interpolation filter comprising a first stage (50), a second stage (52) and a third stage (54). The second stage (52) is comprised of a finite impulse response filter (FIR) that has a nonlinear phase response.

Abstract: The quantization noise in a delta-sigma converter can produce correlated noise when the converter is operating. This correlated noise can produce tones in the frequency band of interest. In a departure from conventional wisdom these tones are substantially eliminated by the degration of the signal-to-noise ratio at the input of the comparator in the delta-sigma converter. In the preferred embodiment this degradation of the signal-to-noise ratio is accomplished by attenuating the input signal to the comparator such that the input signal becomes comparable to the noise generated in the input stage of the comparator.

Abstract: A chopper stabilized analog-to-digital converter includes an analog modulator (10) and a digital filter (12). The analog modulator (10) is comprised of four integrators, a first integrator (20) which is continuous time and the remaining stages of integration (22) which are either continuous or discrete. The first integrator (20) is a chopper stabilized integrator which is comprised of a chopper stabilized differential amplifier (32) which has a single ended output and operates in a continuous time mode. The modulator has a zero that is located at the harmonics of the sampling frequency of the modulator and the chopping clock for the chopper stabilized operation operates at the sampling frequency.

Abstract: An oscillation detect and reset circuit is provided for an analog modulator that includes a first stage of integration having a single ended differential amplifier (32) which is connected to the input of three stages of subsequent integration (40), (42) and (44), in a cascaded configuration. The output of the last stage of integration (44) is connected to the input of a one-bit quantizer (48). The output of the one-bit quantizer (48) is connected to the input of a current (50) feedback, which is connected between a summing node (36) and a negative voltage supply. The summing node (36) sums the current feedback with an input voltage for input to the amplifier (32). Switches (52), (54) and (56) are provided across the inputs and outputs of the integration stages (40), (42) and (44), respectively. The sensing of an unstable condition on the output of second stage of integration (40) is detected by oscillation detect comparators (60) and (62) to initiate a count cycle in a five-bit counter (66).

Abstract: A linear power amplifier having differential push-pull outputs, in which each output consists of an upper and a lower output transistor, includes cross-coupling transistors coupled between the gate of each of the output transistors and a reference voltage such that when the cross-coupled transistor is made conductive, it acts to turn off its associated output transistor. Each of the cross-coupled transistors is controlled by the voltage at the gate of the corresponding output transistor at the other of the differential outputs. Thus, the cross-coupling transistors insure that only one of the upper output transistors is on at one time and only one of the lower output transistors is on at any one time. These cross-coupling transistors operate in conjection with output stage shutoff circuitry to control the current wasted in the output stages of the linear power amplifier by ensuring that the output transistors at each output are not both conducting a significant amount of current at any one time.

Abstract: A semiconductor capacitor for use in an analog-to-digital converter includes two parallel connected capacitors with separate lower plates (44) and (46) fabricated of polycrystalline silicon and upper plates (52) and (54) also fabricated of polysilicon. The plates are separated by capacitive oxide dielectric structures (48) and (50). They are interconnected such that the lower plate (44) of one capacitor is connected to the upper plate (54) of the other capacitor and the lower plate (46) of the other capacitor is connected to the upper plate (52) of the first capacitor. With such a configuration, the odd ordered non-linearities contributing to the voltage coefficient errors are cancelled.

Abstract: Method of operation of an A/D converter having an oversampling front end quantizer coupled to a digital decimation filter. The method includes setting an effective feedback reference voltage to a value that is a predetermined factor greater than a specified maximum analog input voltage; and increasing the gain of the digital decimation filter by an amount substantially equal to the predetermined factor. In accordance with another aspect of the invention, an A/D converter includes a delta-sigma modulator wherein the full-scale analog input voltage is set below a maximum effective feedback reference voltage by a predetermined factor; and, the impulse-response coefficients of a digital decimation filter coupled to the output of the delta-sigma modulator are selected to provide full-scale digital output when a full-scale analog input voltage is applied to the analog voltage input.

Abstract: A method and circuitry for time-sharing a digitally-programmable capacitive element, particularly in conjunction with a switched-capacitor filter circuit. The method includes: selecting a first capacitance value for the capacitive element; initializing the charge on the capacitive element; connecting the capacitive element to first preselected nodes of an electronic circuit; disconnecting the capacitive element from the first preselected nodes of after any charge transfer has substantially been completed; changing the capacitance of the capacitive element to a new desired value; initializing the charge on the capacitive element; and then connecting the capacitive element to other preselected nodes of the electronic circuit. A biquad switched-capacitor filter circuit is configured to use such method in its operation.