Abstract: A clock multiplier/jitter attenuator circuit provides a stable clock which is a multiple frequency of the average frequency of an external digital data stream. The external data is written into successive storage cells of a FIFO at its own clock rate and read out of the FIFO at the rate of an internal clock signal which is formed by frequency dividing the stable clock. The relative locations of the cell being written into and the cell being read out of are determined at periodic time intervals, and these relative locations are used to adjust the frequency of an internal oscillator which generates the stable clock. The instantaneous jitter on the digital data stream is absorbed by the FIFO.

Abstract: Method and circuitry for generating precise reference voltages. The method includes generation of a stair-step voltage waveform wherein the voltage changes from step to step are virtually identical. The stair-step voltage waveform generation includes charging a first capacitor to an available voltage reference and then transferring the charge to a larger second capacitor. This charging and subsequent charge transferring is repetitively performed to generate the stair-step waveform across the terminals of the larger capacitor. Sample-and-hold circuits are used to sample the steps of the stair-step voltage waveform and thereby provide a set of DC reference voltages. The circuitry is suitable for fabrication in a CMOS monolithic integrated circuit and can be used in conjunction with flash A/D converters.

Abstract: A sampling amplifier (22) consisting of a series combination of a signal input terminal (12), a first capacitor (C1), a first amplifier (A1), a second capacitor (C2), a second amplifier (A2), and a signal output terminal (VOUT2) is able to sample at a higher frequency by providing a low impedance path between the signal output terminal (VOUT2) and a junction (VOUT1) between the first amplifier (A1) and the second capacitor (C2) to quasi auto-zero the amplifier between samples.

Abstract: Method for reducing deleterious effects of electrical noise in an analog-to-digital converter wherein both the analog and digital circuitry of the A/D converter are embodied in the same integrated circuit. The method includes sampling an analog input voltage with a first clock signal, generating a second clock signal that is delayed with respect to the first clock signal, and using the second clock signal as a clock for the digital circuitry. In accordance with another aspect of the invention, the method for reducing effects of noise in an A/D converter wherein such noise is generated by a digital decimation filter includes synchronously pipelining the arithmetic operations of the digital decimation filter.

Abstract: A method for adjusting capacitances in a monolithic integrated circuit wherein it is desirable that the capacitances form a binarily-weighted sequence of values includes sequentially-connecting trim capacitors in parallel with a primary capacitor and determining as each trim capacitor is connected, whether the resultant parallel capacitance is larger or smaller than that of a reference capacitance. If the resultant capacitance is too large, the trim capacitor is disconnected, but otherwise is left connected. The process is repeated until each trim capacitor has been tried. For the purpose of adjusting the capacitance of the next-largest capacitance, the final resultant capacitance is connected in parallel with the reference capacitance to form a new reference capacitance. The procedure is then repeated with the next-largest primary capacitor until the final resultant capacitance associated with each primary capacitor has been adjusted.