Patents Assigned to CSMC TECHNOLOGIES FAB2 CO., LTD.
  • Patent number: 12165714
    Abstract: A semiconductor memory, comprising a negative voltage providing unit, which is used for providing a first negative voltage to a word line during a read operation, and comprises: a clamping unit that comprises an input end, a control end and an output end, wherein the input end is coupled to a common ground end of the memory, and the control end is used for receiving a first signal; an energy storage capacitor, a first end of which is coupled to the output end, and a second end that is used for receiving a second signal; and a negative voltage providing end which is coupled to the first end, wherein the clamping unit is used for: pulling the voltage at the output end to the voltage at the input end when the first signal is “0”; and clamping the output end at a clamping voltage when the first signal is “1”.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: December 10, 2024
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD
    Inventors: Bin Chen, Youhui Li, Ming Gu, Xinmiao Zhao, Hao Wang, Shuming Guo, Zongchuan Wang, Nan Zhang
  • Patent number: 12154983
    Abstract: The present disclosure provides a lateral double-diffused metal oxide semiconductor device and a manufacturing method thereof, and an electronic apparatus. The method includes: providing a semiconductor substrate, and forming a drift region and a body region in the semiconductor substrate; forming a drain region in the drift region, forming a source region in the body region, and forming, on the body region, a gate structure extending to the drift region; implanting ions of a first type, so as to form, at a bottom of the drift region, first ion implantation regions extending along a direction from the gate structure to the drain region; forming, above the first ion implantation regions, a plurality of mutually spaced deep trench structures and fin structures between adjacent ones of the deep trench structures; and implanting ions of a second type in the deep trench structures to form second ion implantation regions.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: November 26, 2024
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventor: Nailong He
  • Patent number: 12130649
    Abstract: A bias current generation circuit and a flash memory. The bias current generation circuit includes a voltage source, a switching circuit and a current generation circuit. The voltage source is configured to provide a voltage for generating a bias current. An input terminal of the switching circuit is connected to the voltage source, a control terminal of the switching circuit is configured to receive a control signal. The current generation circuit includes a first MOS transistor and a second MOS transistor, an input terminal and a control terminal of the first MOS transistor are connected to an output terminal of the switching circuit, an output terminal of the first MOS transistor is connected to an input terminal and a control terminal of the second MOS transistor, and an output terminal of the second MOS transistor is grounded.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: October 29, 2024
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Youhui Li, Lijuan Zhu
  • Patent number: 12119395
    Abstract: An insulated gate bipolar transistor, comprising an anode second conductivity-type region and an anode first conductivity-type region provided on a drift region; the anode first conductivity-type region comprises a first region and a second region, and the anode second conductivity-type region comprises a third region and a fourth region, the dopant concentration of the first region being less than that of the second region, the dopant concentration of the third region being less than that of the fourth region, the third region being provided between the fourth region and a body region, the first region being provided below the fourth region, and the second region being provided below the third region and located between the first region and the body region.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: October 15, 2024
    Assignees: SOUTHEAST UNIVERSITY, CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Long Zhang, Jie Ma, Yan Gu, Sen Zhang, Jing Zhu, Jinli Gong, Weifeng Sun, Longxing Shi
  • Publication number: 20240322061
    Abstract: The present disclosure relates to a single-photon avalanche diode integrated with a quenching resistor and a manufacturing method thereof. The method includes: obtaining a wafer; patterning and etching a front surface of the base to form a quenching resistor trench and an isolation trench, wherein a width of the isolation trench is greater than a width of the quenching resistor trench; forming an insulation layer on an inner surface of the quenching resistor trench; depositing polycrystalline silicon on the front surface of the base, where the polycrystalline silicon is filled into the quenching resistor trench and seals the quenching resistor trench while the polycrystalline silicon is filled into the isolation trench and does not seal the isolation trench; performing oxidation treatment on the polycrystalline silicon in the isolation trench; filling a light-shielding conductive material into the isolation trench.
    Type: Application
    Filed: December 13, 2022
    Publication date: September 26, 2024
    Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Zheng BIAN, Kui XIAO, Aifeng ZHAO, Jinjie HU, Tao YANG
  • Publication number: 20240304717
    Abstract: A semiconductor device having a split gate structure and a method for manufacturing the same. The method includes: obtaining a base formed with a trench; forming a trench wall oxide isolation dielectric on the inner surface of the trench, and forming a split gate by filling the trench with a split gate material; forming a first oxide isolation dielectric on the split gate; forming a silicon nitride isolation dielectric on the first oxide isolation dielectric; filling a second oxide isolation dielectric above the split gate in the trench in the position where the silicon nitride isolation dielectric is not formed; and forming a control gate on the second oxidation isolation dielectric. The isolation structure between the split gate and the control gate is a multi-dielectric structure which has a higher gate-source voltage resistance compared to the those using a single layer of oxide dielectric.
    Type: Application
    Filed: August 10, 2021
    Publication date: September 12, 2024
    Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: DONG FANG, KUI XIAO
  • Publication number: 20240304720
    Abstract: The present disclosure involves a semiconductor device and a manufacturing method thereof. A second well region is inserted between first well regions of a semiconductor device to improve the breakdown voltage of the device, and at the same time, the dimension of the upper surface of the second well region in the width direction of the device's conductive channel is set to be smaller than the dimension of the lower surface of the second well region in the width direction of the device's conductive channel to increase the dimension of the upper surface of the adjacent first well region in the width direction of the device's conductive channel. That is, the path width of the current flowing through the upper surface of the drift region is increased when the device is on, and thus the device's on-resistance is reduced.
    Type: Application
    Filed: December 14, 2022
    Publication date: September 12, 2024
    Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Huajun JIN, Liang SONG, Yongshun LI, Mei YUAN, Yanan WANG, Lin LUO, Qiang ZHANG
  • Publication number: 20240282765
    Abstract: The present disclosure provides a GGNMOS transistor structure, an ESD protection device, and an ESD protection circuit. The GGNMOS transistor structure can increase a capability of the ESD protection device to discharge an ESD current per unit size under the action of a P-N-P-N parasitic thyristor formed by an N-potential well, a P-type heavily doped region, and an N-type heavily doped region; the GGNMOS transistor structure can limit a transient peak current of ESD under the action of an equivalent resistor formed by an N-potential well, so that respective GGNMOS transistors of the ESD protection device can conduct uniformly, improving the reliability of the ESD protection circuit.
    Type: Application
    Filed: June 15, 2022
    Publication date: August 22, 2024
    Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Lu HUANG, Yong HUANG, Yan YAN, Wanyi ZHOU, Lin WU, Cheng ZHOU, Haili SHI
  • Publication number: 20240234520
    Abstract: A laterally diffused metal oxide semiconductor device and a preparation method thereof are disclosed. The semiconductor device includes: a substrate; a body region having a first conductivity type and formed in the substrate; a drift region, having a second conductivity type, formed in the substrate and adjacent to the body region; a field plate structure, formed on the drift region, a lower surface of an end of the field plate structure close to the body region being flush with the upper surface of the substrate, and the end of the field plate structure close to the body region also having an upwardly extending inclined surface; and a drain region, having a second conductivity type, formed in an upper layer of the drift region, and in contact with the end of the field plate structure away from the body region.
    Type: Application
    Filed: July 28, 2021
    Publication date: July 11, 2024
    Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: CHUNXU LI, FENG LIN, SHUXIAN CHEN, HONGFENG JIN, HUAJUN JIN, GANG HUANG, YU HUANG, BIN YANG
  • Publication number: 20240222473
    Abstract: The present disclosure provides a DMOS device with a junction field plate and its manufacturing method. A drain region is located on a surface of a semiconductor substrate. A source region is located in the semiconductor substrate at a bottom of a first trench. A gate electrode is located at the bottom of the first trench. The junction field plate improves an effect on reducing surface resistance. At the same time, a depth of trenches in the DMOS device may be reduced, and thereby a depth-to-width ratio of the device is reduced, improving the feasibility of increasing a voltage resistance level. Both the source region and the drain region in the DMOS device are led out on a same surface. A second doped polycrystalline silicon layer includes a first doped sublayer and a second doped sublayer with different conduction types.
    Type: Application
    Filed: December 20, 2022
    Publication date: July 4, 2024
    Applicants: CSMC TECHNOLOGIES FAB2 CO., LTD., SOUTHEAST UNIVERSITY
    Inventors: Feng LIN, Chaoqi XU, Shuxian CHEN, Chunxu LI, Li LU, Siyang LIU, Weifeng SUN
  • Patent number: 12022270
    Abstract: A preparation method for a micro-electromechanical systems (MEMS) microphone includes the steps of: providing a silicon substrate having a silicon surface; forming an enclosed cavity in the silicon substrate; forming a plurality of spaced apart acoustic holes in the silicon substrate, each acoustic hole having two openings, one of which communicating with the cavity and the other one located on the silicon surface; forming a sacrificial layer on the silicon substrate, which includes a first filling portion, a second filling portion and a shielding portion; forming a polysilicon layer on the shielding portion; forming a recess in the silicon substrate on the side away from the silicon surface; and removing the first filling portion, the second filling portion and part of the shielding portion so that the recess is brought into communication with the cavity to form a back chamber, and that the polysilicon layer, the remainder of the shielding portion and the silicon substrate together delimit a hollow chamber,
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: June 25, 2024
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Jiale Su, Guoping Zhou, Xinwei Zhang, Changfeng Xia
  • Patent number: 12015025
    Abstract: A transient voltage suppression device includes: a substrate; a first conductive type well region including a first well and a second well; a second conductive type well region including a third well and a fourth well, the third well being disposed between the first well and the second well so as to isolate the first well and the second well, and the second well being disposed between the third well and the fourth well; a zener diode active region; a first doped region, provided in the first well; a second doped region, provided in the first well; a third doped region, provided in the second well; a fourth doped region, provided in the second well; a fifth doped region, provided in the zener diode active region; and a sixth doped region, provided in the zener diode active region.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: June 18, 2024
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Shikang Cheng, Yan Gu, Sen Zhang
  • Patent number: 12009129
    Abstract: A stacked spiral inductor, comprising: a substrate, and multiple stacked insulating layers and inductive metal layers formed on the substrate by means of a semiconductor process. Each inductive metal layer comprises a conductive coil in a shape of a spiral and a through hole area used for connecting two adjacent inductive metal layers. The conductive coils of the inductive metal layers have a common coil center. In two adjacent inductive metal layers, the conductive coil of the lower inductive metal layer is retracted toward the coil center with respect to the conductive coil of the upper inductive metal layer.
    Type: Grant
    Filed: April 27, 2023
    Date of Patent: June 11, 2024
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventor: Congying Dong
  • Patent number: 11984813
    Abstract: A synchronous rectification control system and method for a quasi-resonant flyback converter are provided. The control system includes a switching transistor voltage sampling circuit configured to sample an output terminal voltage of the switching transistor to obtain a sampled voltage of the switching transistor; a sampling calculation module configured to obtain a dead-time based on the sampled voltage of the switching transistor and a preset relationship, the preset relationship being a correspondence between the duration of the sampled voltage of the switching transistor being below a first preset value and the dead-time during an on-time of a switching cycle of the switching transistor, the dead-time being a time from when the switching transistor is turned off to when the synchronous rectification transistor is turned on; and a control module configured to receive the dead-time and control switching of the synchronous rectification transistor based on the dead-time.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: May 14, 2024
    Assignees: SOUTHEAST UNIVERSITY, CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Shen Xu, Siyu Zhao, Congming Qi, Sen Zhang, Xiaoyu Shi, Weifeng Sun, Longxing Shi
  • Publication number: 20240136413
    Abstract: A laterally diffused metal oxide semiconductor device and a preparation method thereof are disclosed. The semiconductor device includes: a substrate; a body region having a first conductivity type and formed in the substrate; a drift region, having a second conductivity type, formed in the substrate and adjacent to the body region; a field plate structure, formed on the drift region, a lower surface of an end of the field plate structure close to the body region being flush with the upper surface of the substrate, and the end of the field plate structure close to the body region also having an upwardly extending inclined surface; and a drain region, having a second conductivity type, formed in an upper layer of the drift region, and in contact with the end of the field plate structure away from the body region.
    Type: Application
    Filed: July 27, 2021
    Publication date: April 25, 2024
    Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: CHUNXU LI, FENG LIN, SHUXIAN CHEN, HONGFENG JIN, HUAJUN JIN, GANG HUANG, YU HUANG, BIN YANG
  • Patent number: 11923453
    Abstract: The present invention relates to an LDMOS device and a method for preparing same. When a field plate hole is formed by etching an interlayer dielectric layer, the etching of the field plate hole is stopped on a blocking layer by means of providing the blocking layer between a semiconductor base and the interlayer dielectric layer. Since the blocking layer is provided with at least one layer of an etch stop layer, and steps are formed on the surface of the blocking layer, at least two levels of formed hole field plates are distributed in a step shape, and lower ends of the first level of hole field plates to the nth level of hole field plates are gradually further away from the drift area in the direction from a gate structure to a drain area.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: March 5, 2024
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Huajun Jin, Chunxu Li
  • Patent number: 11894458
    Abstract: A lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS), including: a trench gate including a lower part inside a trench and an upper part outside the trench, a length of the lower part in a width direction of a conducting channel being less than that of the upper part, and the lower part extending into a body region and having a depth less than that of the body region; an insulation structure arranged between a drain region and the trench gate and extending downwards into a drift region, a depth of the insulation structure being less than that of the drift region.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: February 6, 2024
    Assignees: SOUTHEAST UNIVERSITY, CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Jiaxing Wei, Qichao Wang, Kui Xiao, Dejin Wang, Li Lu, Ling Yang, Ran Ye, Siyang Liu, Weifeng Sun, Longxing Shi
  • Patent number: 11887979
    Abstract: A transient voltage suppression device and a manufacturing method therefor, the transient voltage suppression device including: a substrate, a first conductivity type well region and a second conductivity type well region disposed in the substrate. The first conductivity type well region includes a first well, a second well, and a third well. The second conductivity type well region includes a fourth well that isolates the first well from the second well, and a fifth well that isolates the second well from the third well. The device further includes a Zener diode well region provided in the first well, a first doped region provided in the Zener diode well region, a second doped region provided in the Zener diode well region, a third doped region provided in the second well, a fourth doped region provided in the third well, and a fifth doped region provided in the third well.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: January 30, 2024
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Shikang Cheng, Yan Gu, Sen Zhang
  • Patent number: 11777416
    Abstract: A flyback converter and an output voltage acquisition method therefor and apparatus thereof, wherein the output voltage acquisition method comprises the following steps: acquiring the reference output voltage of a flyback converter; sampling the current output voltage of the flyback converter within a reset time of each switching period among M continuous switching periods of the flyback converter, wherein M is a positive integer; and according to the reference output voltage and the current output voltage, sampling a dichotomy to successively approximate the current output voltage until the M switching periods are finished, and acquiring the output voltage of the flyback converter.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: October 3, 2023
    Assignees: SOUTHEAST UNIVERSITY, CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Weifeng Sun, Huaxin Zhang, Hu Zhang, Menglin Yu, Siyu Zhao, Shen Xu, Longxing Shi
  • Patent number: 11770076
    Abstract: Disclosed are a system and method for controlling an active clamp flyback (ACF) converter. The system includes: a drive module configured to control turning-on or turning-off of a main switching transistor SL and a clamp switching transistor SH; a main switching transistor voltage sampling circuit configured to sample a voltage drop between an input terminal and an output terminal of the main switching transistor SL; a first comparator connected to the main switching transistor voltage sampling circuit and configured to determine whether a sampled first sampling voltage is a positive voltage or a negative voltage; and a dead time calculation module configured to adjust, according to an output of the first comparator and a main switching transistor control signal DUTYL of a current cycle, a clamp switching transistor control signal DUTYH of next cycle outputted by the drive module.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: September 26, 2023
    Assignees: SOUTHEAST UNIVERSITY, CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Shen Xu, Minggang Chen, Wanqing Yang, Dejin Wang, Rui Jiang, Weifeng Sun, Longxing Shi