Abstract: A semiconductor device, having an electro-static discharge (ESD) protection structure, comprises: a diode, connected between a gate and a source of the semiconductor device, and comprising a diode main body, and two connection portions, respectively connected to two terminals of the diode main body and respectively electrically connected to the gate and the source; and a substrate comprising two insulation pads disposed thereon and separated from each other. A surface of the substrate between the insulation pads is provided with an insulation layer. The diode main body is arranged on the insulation layer. The two connection portions are configured to extend, respectively, from either end of the diode main body to the insulation pad on the corresponding side. A dielectric layer is arranged on the diode and the two insulation pads, and a metal conduction line layer is arranged on the dielectric layer.

Abstract: A signal amplification circuit comprises a low pass filter circuit (100). The low pass filter circuit (100) comprises two input ends and two output ends and further comprises two capacitors (C1, C2) having opposite polarities respectively connected between two output ends. A buffer circuit (200) comprises two input ends, a first operational amplifier (A1) and a second operational amplifier (A2), two output ends and a plurality of switches. A switched capacitor integrated circuit (300) comprises two input ends, a third operational amplifier (A3), a plurality of capacitor modules, a plurality of chopper modulators and two output ends. A signal switch (S) is used to control the on and off states of voltage signal before amplification.

Abstract: A switch control circuit includes: a clock circuit (110) configured to generate a first clock control signal (CLK1) and a second clock control signal (CLK2); a voltage boosting circuit (120) configured to receive the second clock control signal (CLK2) and an operating voltage outputted by the power source (VDD); and boost the operating voltage by a preset value to form a switch control signal (H1) under the control of the second clock control signal (CLK2); and an inverting circuit (130) configured to receive the first clock control signal (CLK1) and the switch control signal (H1), and determine whether or not to output the switch control signal (H1) to the switch circuit according to the first clock control signal (CLK1), so as to control on/off of the switch circuit.

Abstract: An optical proximity correction method, comprising: dissecting an edge of a design pattern (120/220) to form a segment (Seg1/Seg2); setting target points of the segments (Seg1/Seg2), and if the segments (Seg1/Seg2) translate in a direction vertical to the segments (Seg1/Seg2), controlling tangent points (P1/P2) of the segments (Seg1/Seg2) tangent to a simulated pattern (110/210) to coincide with the target points; computing edge position differences of the target points; and correcting the design pattern (120/220) according to the edge position differences.

Abstract: An accelerator comprises: an accelerometer (100), configured to detect an acceleration of a motion of a carrier and output a corresponding electrical signal; a sampling and low-pass filter (200), coupled to the accelerometer (100), and configured to sample the electrical signal regularly and filter a noise from the electrical signal; an amplifier (300), configured to amplify the electrical signal after filtering the noise; an analog-to-digital converter (400), configured to convert the amplified electrical signal into a digital signal; a function control module (500), configured to process the digital signal and output a control signal to control the analog-to-digital converter (400), the amplifier (300), and the sampling and low-pass filter (200); and an oscillator module (600), configured to output, according to the control signal, a sampling signal to the sampling and low-pass filter (200), so as to control the sampling and low-pass filter (200) to sample the electrical signal regularly.

Abstract: Provided is a laterally diffused metal-oxide-semiconductor field-effect transistor, comprising a substrate (110), a source (150), a drain (140), a body region (160), a P-type field-limiting ring (135), and a well region on the substrate (110); the well region comprises an inserted well (122), which has P-type doping and is disposed below the drain and connected to the drain; N wells (124) disposed at the two sides of the inserted well (122); a P well (126) disposed next to the N well (124) and connected to the N well (124); a P-type field-limiting ring (135), which is disposed inside the N well (124), is a closed ring-shaped structure, and is located at the periphery below the drain (140); the inserted well (122) extends in its longitudinal direction to the position where it is in contact with said P-type field-limiting ring (135); the source (150) and the body region (160) are disposed inside the P well (126).

Abstract: A signal amplification circuit comprises a low pass filter circuit (100). The low pass filter circuit (100) comprises two input ends and two output ends and further comprises two capacitors (C1, C2) having opposite polarities respectively connected between two output ends. A buffer circuit (200) comprises two input ends, a first operational amplifier (A1) and a second operational amplifier (A2), two output ends and a plurality of switches. A switched capacitor integrated circuit (300) comprises two input ends, a third operational amplifier (A3), a plurality of capacitor modules, a plurality of chopper modulators and two output ends. A signal switch (S) is used to control the on and off states of voltage signal before amplification.

Abstract: A lithography stepper alignment and control method, comprising: providing a test template having a plurality of field sizes, and deriving a set of overlay values for each field size (S1); calculating a set of compensation amounts for the overlay value of each field size (S2); and, comparing a set of estimated alignment compensation values for a product with each compensation amount for each field size, selecting as the product alignment compensation values the set of compensation amounts of a field size closest to the set of estimated alignment compensation values, and, using the product alignment compensation values to perform alignment compensation on said product (S3).

Abstract: An MEMS double-layer suspension microstructure manufacturing method, comprising: providing a substrate (100); forming a first dielectric layer (200) on the substrate (100); patterning the first dielectric layer (200) to prepare a first film body (210) and a cantilever beam (220) connected to the first film body (210); forming a sacrificial layer (300) on the first dielectric layer (200); patterning the sacrificial layer (300) located on the first film body (210) to make a recess portioned portion (310) for forming a support structure (420), with the first film body (210) being exposed at the bottom of the recess portioned portion (310); forming a second dielectric layer (400) on the sacrificial layer (300); patterning the second dielectric layer (400) to make the second film body (410) and the support structure (420), with the support structure (420) being connected to the first film body (210) and the second film body (410); and removing part of the substrate under the first film body (210) and removing the

Abstract: A method for preparing a trench isolation structure, which comprises the following steps of: providing a substrate; forming an oxide layer on the substrate; successively generating an oxidation barrier layer and an ethyl orthosilicate layer on the surface of the oxide layer; etching the oxidation barrier layer and the ethyl orthosilicate layer; corroding the substrate to form a trench by using the oxidation barrier layer and the ethyl orthosilicate layer as mask layers; removing the ethyl orthosilicate layer, and oxidizing a side wall of the trench by using the oxidation barrier layer as a barrier layer; filling the trench with a polysilicon and then etching back the polysilicon, and removing the polysilicon on the surface of the oxidation barrier layer; and removing the oxidation barrier layer and the oxide layer on the surface of the substrate.

Abstract: An electrostatic protection device of an LDMOS silicon controlled structure comprises a P-type substrate (310), an N-well (320) and a P-well (330) on the substrate, a gate electrode (340) overlapping on the P-well (330) and extending to an edge of the N-well (320), a first N+ structure and a first P+ structure provided in the N-well (320), and a second N+ structure and a second P+ structure provided in the P-well(330), the first N+ structure being a drain electrode N+ structure (322), the first N+ structure being a drain electrode N+ structure (322), the first P+ structure being a drain electrode P+ structure (324), the second N+ structure being a source electrode N+ structure (332), the second P+ structure being a source P+ structure (334), and a distance from the drain electrode P+ structure (324) to the gate electrode (340) being greater than a distance from the drain electrode N+ structure (322) to the gate electrode (340).

Abstract: A test pattern for testing a trench POLY over-etched step is provided. The test pattern is a trench (14) formed on a substrate (1); the trench (14) comprises a bottom surface and two side surfaces extending from the bottom surface; the trench (14) is formed on the substrate (1) with a preset angle of non-90° formed between the longitudinal direction (L) thereof and the longitudinal direction (X) of a wafer scribing trench. The test pattern can extend the scanning length of a step scanning equipment without changing the width of the trench.

Abstract: The present invention relates to a method for manufacturing a laterally insulated-gate bipolar transistor, comprising: providing a wafer having an N-type buried layer (10), an STI (40), and a first N well (22)/a first P well (24) which are formed successively from above a substrate; depositing and forming a high-temperature oxide film on the first N well (22) of the wafer; performing thermal drive-in on the wafer and performing photoetching and etching on the high-temperature oxide film to form a mini oxide layer (60); performing photoetching and ion implantation so as to form a second N well (32) inside the first N well (22) and second P wells (34) inside the first N well (22) and the first P well (24); then successively forming a gate oxide layer and a polysilicon gate (72), wherein one end of the gate oxide layer and the polysilicon gate (72) extends onto the second P well (34) inside the first N well (22), and the other end extends onto the mini oxide layer (60) on the second N well (32); and photoetching

Abstract: A preparation method for a flat cell ROM device, comprising the steps of: providing a substrate, and forming a P well on the substrate; forming a photomask layer on the P well and performing photoetching to form an injection window; injecting P-type ions in the formed injection window to form a P-type region; injecting N-type ions in the injection window so as to form an N-type region on the P-type region; and forming a gate oxide layer and a poly-silicon gate so as to complete the preparation of a device.

Abstract: A testing structure of a strip width of a scribing slot is provided, the structure includes a first isolated line (232) and a second isolated line (234) which are perpendicular to each other, the testing structure further includes a first field region pattern (220), the first field region pattern (220) includes two graphics, the two graphics are each located on one side of the first isolated line (232) and opposite to each other. A testing method of a strip width of a scribing slot is also disclosed.

Abstract: A chemical-mechanical polishing process using a silicon oxynitride anti-reflection layer (S340) includes: (S1) providing a semiconductor wafer comprising a substrate (S310), an oxidation layer (S320) formed on the substrate (S310), a silicon nitride layer (S330) formed on the oxidation layer (S320), an anti-reflection layer (S340) formed on the silicon nitride layer (S330), a trench extending through the anti-reflection layer (S340) and into the substrate (S310), and a first silicon dioxide layer (S350) filling the trench and covering the anti-reflection layer (S340); (S2) polishing the first silicon dioxide layer (S350) until the anti-reflection layer (S340) is exposed; (S3) removing the anti-reflection layer (S340) by dry etching; (S4) forming a second silicon dioxide layer (S360) on the surface of the semiconductor wafer from which the anti-reflection layer (S340) is removed; (S5) polishing the second silicon dioxide layer (S360) until the silicon nitride layer (S330) is exposed; (S6) and, removing the sil

Abstract: A test method and system for cut-in voltage. The method comprises: coarse scanning of the cut-in voltage: a grid voltage, i.e., the cut-in voltage, is quickly determined when a drain terminal current is greater than a target current for the first time (100); accurate scanning of the cut-in voltage: a scanning step length is shortened continuously until the scanning step length is shorter than a preset step length, and each time the scanning step length is shortened, the scanning is conducted according to the current shortened scanning step length on the basis of the cut-in voltage determined in the former time, and then the cut-in voltage under the condition of the current shortened scanning step length is determined again (200). The scanning voltage is automatically increased or decreased by the test method and system through adding high resolution and high precision test conversion into a second scanning test, and therefore the testing of the cut-in voltage becomes more efficient and more accurate.

Abstract: A chemical-mechanical polishing process using a silicon oxynitride anti-reflection layer (S340) includes: (S1) providing a semiconductor wafer comprising a substrate (S310), an oxidation layer (S320) formed on the substrate (S310), a silicon nitride layer (S330) formed on the oxidation layer (S320), an anti-reflection layer (S340) formed on the silicon nitride layer (S330), a trench extending through the anti-reflection layer (S340) and into the substrate (S310), and a first silicon dioxide layer (S350) filling the trench and covering the anti-reflection layer (S340); (S2) polishing the first silicon dioxide layer (S350) until the anti-reflection layer (S340) is exposed; (S3) removing the anti-reflection layer (S340) by dry etching; (S4) forming a second silicon dioxide layer (S360) on the surface of the semiconductor wafer from which the anti-reflection layer (S340) is removed; (S5) polishing the second silicon dioxide layer (S360) until the silicon nitride layer (S330) is exposed; (S6) and, removing the sil

Abstract: An embodiment of a NOR Flash device manufacturing method includes: providing a substrate having a first polycrystalline silicon layer disposed thereon; forming a first hard mask layer on the first polycrystalline silicon layer; etching the first hard mask layer to form a first opening, and cleaning a gas pipeline connected to an etching cavity before etching the first hard mask layer; forming a second hard mask layer on the first hard mask layer, and the second hard mask layer covers the bottom and side wall of the first opening; etching the second hard mask layer to form a second opening, the width of the second opening is smaller than the width of the first opening; etching the first polycrystalline silicon, forming a floating gate. The NOR Flash device manufacturing method improves the yield of the NOR Flash device.

Abstract: The present invention provides a method of forming a passivation layer of a MOS device, and a MOS device. The method of forming a passivation layer of a MOS device includes: forming a substrate; forming a dielectric on the substrate; patterning the dielectric to expose a part of the substrate; forming a metal on the exposed part of the substrate, and the dielectric; forming a TEOS on the metal; forming a PSG on the TEOS; and forming a silicon nitrogen compound on the PSG. Therefore, the cracks problem of the passivation can be alleviated.