Abstract: An apparatus having a plurality of power supply domains and a plurality of logic components. Each of the plurality of logic components residing within a different one of the plurality of power supply domains. Each of the plurality of logic components is configured to operate with a corresponding clock signal within a respective one of the plurality of power supply domains.

Abstract: Power management commands are provided to a power management unit of a processing device, wherein the power management unit coupled to a core system block of the processing device. Sampling of the core system block is performed in response to the power management commands by the power management unit, wherein sampling includes periodically powering the core system block.

Abstract: A method and a system for supplying power to a microcontroller with a single cell. One embodiment of the present invention discloses incorporation of a power supply pump circuit with the microcontroller and their dynamic interaction. The microcontroller sends its power requirements to the power supply pump circuit and in response, the power supply pump circuit controls the operating voltage with optimal efficiency. The dynamic update of power supply pump circuit results in an efficient use of the power supply pump circuit and thus results in a reduction of the number of dry cell batteries to only a single cell. Incorporation of the microcontroller and power supply pump circuit onto a single chip reduces the pin number requirements as well as the space required on the printed circuit board.

Abstract: A system and method for programming and erasing a semiconductor memory is disclosed. More particularly, the present invention uses the bit lines of a volatile memory portion of semiconductor memory so as to program and erase the non-volatile portion of the semiconductor memory.

Abstract: A high-speed redundancy circuit having redundant rows/blocks for replacing defective rows, columns and blocks. For row redundancy, an off-pitch encoder in conjunction with row control circuitry is used to disable defective rows while enabling non-defective rows. An off-pitch fuse is blown to enable redundant rows for a particular sub-array. Therefore, the enabled redundant row replaces the disabled defective row. For column/block redundancy, an encoder is used where appropriate off-pitch fuses are blown to enable the appropriate redundant blocks. Unlike row redundancy, the defective columns/blocks are not disabled. Instead when redundant blocks are enabled, the column/block control unit detects whether to transfer data to/from the redundant block/columns or block/columns corresponding to the defective columns. As a result of using off-pitch fuses the die size is reduced.

Abstract: A phase locked loop circuit, system, and method of operation are provided. The phase-locked loop (PLL) includes a first PLL and a second PLL. The first PLL is nested inside the second PLL. According to one embodiment, the first PLL is coupled to the output of a surface acoustic wave (SAW) resonator, and includes first divider coupled within a feedback loop of the first PLL. The second PLL is coupled between an input of the overall PLL circuit, and output from the first PLL and the first divider. According to a second embodiment, the second PLL includes a SAW voltage-controlled oscillator (VCSO) and a second divider coupled to an output of the first PLL. Regardless of whether the first or second embodiments are contemplated, the nested first and second PLL circuits provide an agile, low phase noise, clock synthesizer and jitter attenuator hereof.

Abstract: A correlator has a feedback circuit having a first input coupled to an incoming data stream, a second input and an output. A data register is to store an incoming data stream having a number of candidate bits, the data register having an output coupled to the second input of the feedback circuit. A code register is to store a known code having a predetermined number of code bits and a comparator is to compare a portion of the incoming data stream to a portion of the known code.

Abstract: A multiplexer circuit provided herein includes a plurality of pass devices coupled in parallel between a power supply and a ground supply. According to one embodiment, each pass device may include a first pair of transistors, which is coupled in series between the power supply and the ground supply, and a second pair of transistors, which is coupled to the first pair of transistors for controlling a current passed there through. In general, the second pair of transistors may be configured for increasing the amount of current passed through the first pair of transistors. For example, the second pair of transistors may utilize a bootstrapping effect to increase a pair of control voltages supplied to the gate terminals of the first pair of transistors. The increased control voltages function to over-drive the gate terminals of the first pair of transistors, thereby increasing the amount of current passed there through.

Abstract: A circuit and method are provided herein for monitoring the status of a clock signal. In general, the method may include supplying a pair of clock signals to a clock monitor circuit, which is configured for monitoring a status of one clock signal relative to the other. The status indicates whether the frequency of the one clock signal is faster, slower or substantially equal to the frequency of the other clock signal. Once determined, the status may be stored as a bit pattern within a status register, which is operatively coupled to the clock monitor circuit. This enables the status to be read by detecting a logic state of one or more bits within the status register.

Abstract: The circuit comprises a pulse width modulated (PWM) input signal, a resistor, an instrumentation amplifier, a filter and an analog to digital converter. The method of performing synchronization comprises sampling an analog signal and forming a digital data stream representing the signal, filtering the data stream to remove harmonics, measuring an approximate level of ripple in the data stream, detecting a change in the level of ripple, and based upon change in the level of ripple, determining if a stall has occurred.

Abstract: A method of forming structures comprises depositing silicon nitride films simultaneously on a plurality of substrates at a first temperature, and heating the silicon nitride films at a temperature greater than the first temperature.

Abstract: A method of transmitting communications codes is used in spread spectrum communications systems. The method includes transmitting a first pseudo-noise code, and transmitting a second pseudo-noise code, wherein the second pseudo-noise code is a time-reversed version of the first pseudo-noise code. A device includes a first shift register to store a first code and a second register to store a second code in a time-reversed version. A comparison circuit then compares the two codes and a result is output.

Abstract: A method and system is provided for supplying power to a host via a USB port. The power is transmitted to the host using the standard VBUS and GND lines that are part of standard USB cables and connectors. The peripheral device includes a special USB descriptor block. During the standard enumeration process, the host reads this USB descriptor block and recognizes that the device can provide power to the host. A set feature command is used to start the power transmission to the host.

Abstract: An apparatus includes a configuration memory coupled to one or more structural arithmetic elements, the configuration memory to store values that cause the structural arithmetic elements to perform various functions. The apparatus also includes a system controller to dynamically load the configuration memory with values, and to prompt the structural arithmetic elements to perform functions according to the values stored by the configuration memory.

Abstract: A system comprises a temperature sensor generate multiple base-emitter voltage signals by sequentially providing various currents to a transistor, and a system controller to determine a differential voltage signal according to the multiple base-emitter voltage signals, the differential voltage signal proportional to an environmental temperature associated with the transistor.

Abstract: Embodiments of the invention relate to a method and apparatus to drive non-resistive loads. The non-resistive load driver may include two or more drivers, such as a high-drive circuit and a low-drive circuit, to drive rail-to-rail output voltages and to stabilize the output voltages at a substantially constant level. The high-drive circuit may drive the output voltage of the non-resistive load driver to a threshold level, whereas the low-drive circuit may modify the output voltage of the non-resistive load driver to approximate an input voltage of the non-resistive load driver, and compensate any leakage associated with the non-resistive loads to provide a substantially constant output voltage. The low-drive circuit consumes less current than the high-drive circuit. The non-resistive load driver consumes less power and use less chip space.

Abstract: A memory device includes a memory array having a plurality of memory cells arranged in a row-column format, where the memory array is configured to designate at least one of the memory cells as a test memory cell. The memory system also includes a sense amplifier to read the test memory cell and to evaluate a validity of the memory array responsive to reading the test memory cell.

Abstract: Embodiments of the invention relate to a method and apparatus to reduce power consumption in a passive matrix LCD driver circuit by using a plurality of drive buffers and active power management of sub-blocks in the passive matrix LCD drive circuit. Each drive buffer may operate in a first phase, which may include a high-drive mode to drive an LCD voltage to a threshold voltage level and a low-drive mode to modify the LCD voltage to approximate an input voltage of the drive buffer, and to maintain a constant LCD voltage level. The low-drive buffer consumes less current than the high-drive buffer, thus reducing power consumption. The drive buffer may also operate in a second phase, also a no-drive mode, in which the drive buffer and the bias voltage generator may be completely turned off, to further reduce power consumption. The drive buffer may be used to drive capacitive loads, as well as partially-resistive loads and inductive loads.

Abstract: A universal serial bus controller pre-generates and stores a subset of USB commands in a memory, the pre-generated commands available for transmission to at least one USB peripheral device over universal serial bus, and transfers at least one command from the subset of pre-generated commands stored in the memory to the USB peripheral device over the universal serial bus. The universal serial bus controller may receive a response to the transferred command from the USB peripheral device over the universal serial bus, and send an acknowledgment packet to the USB peripheral device over the universal serial bus responsive to receiving the response from the USB peripheral device.

Abstract: A system includes at least one word line decoder to select word lines to activate, and a memory cell array having a plurality of memory cell devices to store data received through one or more write bit lines. At least one of the memory cell devices including a memory cell to store data received over one or more write bit lines, and a sensing inversion device coupled to the memory cell and word lines. The sensing inversion device can read data stored by the memory cell and provide the read data to one or more read bit lines when at least one of the word lines is activated for read operations.