Patents Assigned to Cypress Semiconductor Corp.
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Patent number: 7280574Abstract: A circuit for driving a laser diode has a variable bias circuit. The variable bias circuit has an output designed to couple to the laser diode. A modulation circuit has an output designed to couple to the laser diode.Type: GrantFiled: May 15, 2002Date of Patent: October 9, 2007Assignee: Cypress Semiconductor Corp.Inventors: Vijay Khawshe, Gajender Rohilla
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Patent number: 7279925Abstract: A buffer circuit, system, and method are provided. The buffer circuit includes a control circuit coupled to an output of the buffer, or possibly to an output of the first stage of a buffer. A pre-charge circuit is also provided coupled to bias an input of the control circuit to a voltage value approximately near a threshold voltage of the control circuit. The pre-charge bias amount is slightly less than the amount needed to place the control circuit in a high current conduction state. A coupling circuit is thereafter used and adapted to couple an input voltage applied to the buffer circuit to the input of the control circuit. This causes the control circuit to enter the high current conduction state. Depending on the input impedance of the coupling circuit, by pre-charging the coupling circuit input, less time is needed to cause the coupling circuit to enter and thereafter leave a high current conduction state.Type: GrantFiled: March 1, 2006Date of Patent: October 9, 2007Assignee: Cypress Semiconductor Corp.Inventors: Greg Richmond, Paula O'Sullivan
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Patent number: 7279981Abstract: A unity gain amplifier has a current mirror. A compensation circuit has an input coupled to an output of the current mirror. An output transistor has a base coupled to the output of the current mirror and a source of the output transistor is coupled to an output of the compensation circuit. The compensation circuit has a resistor in series with a capacitor.Type: GrantFiled: August 24, 2004Date of Patent: October 9, 2007Assignee: Cypress Semiconductor Corp.Inventor: Gary Peter Moscaluk
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Publication number: 20070222684Abstract: System and method for a multi-layer antenna is shown and described. A multi-layer antenna includes a plurality of antenna layers that are stacked and aligned to minimize an antenna footprint without degrading electrical performance. This reduced antenna footprint allows system designer the ability to reduce the overall size of wireless communication devices incorporating the multi-layer antenna.Type: ApplicationFiled: March 13, 2007Publication date: September 27, 2007Applicant: CYPRESS SEMICONDUCTOR CORP.Inventor: Philip P. Kwan
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Patent number: 7275119Abstract: A bus architecture includes master devices that are each capable of initiating a data transfer procedure by generating a bus request signal. Each of the master devices is arranged to transmit an address signal to an address input of a multiplexer, to transmit a data signal to a data input of the multiplexer, and to transmit a control signal to a control input of the multiplexer. The control signals may include burst type control signals. The multiplexer is capable of selectively coupling a selected master device chosen from the group consisting of the master devices to a bus. The bus architecture further includes an arbiter arranged to receive the bus request signals as first inputs and arranged to receive the burst type control signals as second inputs, where the burst type control signals are received from an ingress side of the multiplexer.Type: GrantFiled: August 14, 2006Date of Patent: September 25, 2007Assignee: Cypress Semiconductor Corp.Inventor: Gordon R. Clark
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Publication number: 20070220150Abstract: A convenient, low-cost method is provided herein for switching between one or more source devices, which are connected to a sink device via a multimedia interface. According to one embodiment, the method described herein may be used for switching between a plurality of source devices compatible with the High Definition Multimedia Interface (HDMI™) or any other similar audio/video interfaces. In some cases, the method may utilize priority data to connect the source device having the highest priority to the sink. In other cases, the method may allow manual/remote selection to override an original source selection based on priority.Type: ApplicationFiled: February 28, 2007Publication date: September 20, 2007Applicant: CYPRESS SEMICONDUCTOR CORP.Inventor: Gopal K. Garg
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Publication number: 20070213887Abstract: A wireless tracking device including a positioning system for determining a location of the device and a processor connected to the positioning system. The wireless tracking device further including a wireless radio connected to the processor for transmitting the location of the device across a wireless area network. A vehicle monitoring system including a sensor, a microcontroller configured to receive a sensor input from the sensor and determine a vehicle condition data, and a wireless transmitter in communication with the microcontroller. The wireless transmitter is configured to transmit the vehicle condition data to a remote data network access point. A method of monitoring a vehicle including determining a status of the vehicle, locating an available wireless data network access point, and transmitting the status of the vehicle though the access point.Type: ApplicationFiled: December 5, 2006Publication date: September 13, 2007Applicant: CYPRESS SEMICONDUCTOR CORP.Inventor: Ryan Woodings
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Patent number: 7264975Abstract: A method for fabricating a magnetic random access memory circuit (MRAM) and a MRAM circuit resulting therefrom are provided. The method includes depositing a first conductive layer upon and in contact with a plurality of magnetic cell junctions and selectively removing portions of the first conductive layer arranged above the plurality of magnetic cell junctions. In addition, the method includes depositing a second conductive layer above remaining portions of the first conductive layer and the plurality of magnetic cell junctions. The resulting circuit may include a field-inducing line having thickness and/or width variations relative to underlying magnetic cell junctions.Type: GrantFiled: September 14, 2004Date of Patent: September 4, 2007Assignee: Cypress Semiconductor Corp.Inventor: John W. Tiede
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Publication number: 20070200518Abstract: A system and method for bi-directional communication between a system controller and a fan controller: The system operates in two modes and there are two communication paths between the system controller and the fan controller. The first communication path provides a PWM signal the frequency of which indicates the mode in which the system is operating. During the first mode, the duty cycle of the PWM signal on the first signal path indicates the desired fan speed. In the first mode, the second communication path carries a conventional tachometer signal. In the second mode the second communication path operates as a bi-directional communications signal path between said system controller and said fan controller.Type: ApplicationFiled: November 14, 2006Publication date: August 30, 2007Applicant: CYPRESS SEMICONDUCTOR CORP.Inventor: Greg Verge
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Patent number: 7253094Abstract: A method for processing a semiconductor topography which includes removing metal oxide layers from the bottom of contact openings is provided. In some embodiments, the method may include etching openings within a dielectric layer to expose conductive and silicon surfaces within the semiconductor topography is provided. In such cases, the method further includes exposing the semiconductor topography to an etch process adapted to remove metal oxide material from the conductive surfaces without substantially removing material from the silicon surfaces. In some cases, the etch chemistry used for the etch process may include sulfuric acid. In addition or alternatively, the etch chemistry may include hydrogen peroxide. In any case, the etch chemistry may be distinct from chemistries used to remove residual matter generated from the etch process used to form the openings within the dielectric and/or the removal of the masking layer used to pattern the openings.Type: GrantFiled: November 19, 2004Date of Patent: August 7, 2007Assignee: Cypress Semiconductor Corp.Inventors: Jie Zhang, Vinay Krishna, Chan-Lon Yang
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Publication number: 20070164789Abstract: An improved level shift circuit and method for level shifting is disclosed herein. In general, the improved level shift circuit adds a pulse generator, a feedback transistor and a latch to a conventional cross-coupled level shift circuit configuration. The pulse generator and feedback transistor are configured for reducing a fall delay associated with the level shift circuit. For example, the pulse generator is coupled for supplying a short duration feedback pulse to the feedback transistor during a first time period when input and output signals of the level shift circuit transition to a LOW state. The feedback pulse reduces the fall delay by increasing the speed with which the output signal is pulled LOW. The latch is coupled for preventing the feedback signal from floating when at least one of the input and output signals is HIGH. An integrated circuit comprising at least one level shift circuit is also contemplated herein.Type: ApplicationFiled: January 17, 2007Publication date: July 19, 2007Applicant: CYPRESS SEMICONDUCTOR CORP.Inventors: Geeta Panjwani, Aparna Jandhyala, Derwin Mattos
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Patent number: 7245162Abstract: An output stage circuit may include a sourcing driver device, a nonlinear local feedback loop having a feedback transistor and a first current mirror, a sinking driver device, and an output signal. The output stage circuit may actively and dynamically adjust the transconductance of the sourcing driver device by sensing its region of operation, and by sending a nonlinear feedback signal through the local feedback loop and the first current mirror. The nonlinear local feedback loop may be used for control and headroom compensation of the sourcing driver transistor to provide low distortion operation using a smaller size driver transistor.Type: GrantFiled: September 17, 2004Date of Patent: July 17, 2007Assignee: Cypress Semiconductor Corp.Inventor: Richard F. Betts
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Patent number: 7245725Abstract: A dual processor framer includes a receiver and a transmitter which share common circuitry and/or code. Separate direct memory access controllers may be used for each of the receiver and transmitter. Processing is distributed over two or more processors. One processor may be a lower power processor while another processor may be a higher power processor. At least one of the two or more processors may be programmable or reconfigurable. The transceiver is configured to provide internal loop back self testing at various points in the processing. Timing within the transceiver may be established almost entirely by a single clock domain.Type: GrantFiled: May 17, 2002Date of Patent: July 17, 2007Assignee: Cypress Semiconductor Corp.Inventor: Paul Beard
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Patent number: 7239178Abstract: A voltage level translation circuit includes a first power supply voltage, a second power supply voltage, wherein the second supply voltage is lower than the first supply voltage, a low voltage input, wherein the low voltage input is referenced from the second supply voltage, a resistive element leaker transistor having a source and a drain, wherein the source is coupled to the first power supply voltage, a PMOSFET having a gate and a source, wherein the source is coupled to the first power supply voltage, and a pulse generator coupled to the gate of the PMOSFET, wherein the pulse generator is capable of controlling the operation of the PMOSFET.Type: GrantFiled: March 23, 2005Date of Patent: July 3, 2007Assignee: Cypress Semiconductor Corp.Inventors: Charles A. Cornell, Matthew S. Berzins, Stephen M. Prather
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Patent number: 7230971Abstract: The present invention is a method and apparatus for providing a pseudo random sequence for a spread spectrum system that prevents interception and provides real estate and power consumption efficiency. A pseudo random sequence may be created in real-time by associating a pseudo random sequence of a channel location of the carrier frequency at an instant in time. For example, the entire band of the spread spectrum system may be scanned to detect a channel with a low received signal strength. The location of the channel, or the actual frequency of the channel, could be associated with a particular pseudo random sequence to create a hop set for frequency hopping. Additionally, the location of a characteristic of the spread spectrum system, such as a noise characteristic, could be utilized to determine a content of a pseudo random sequence.Type: GrantFiled: May 17, 2002Date of Patent: June 12, 2007Assignee: Cypress Semiconductor Corp.Inventor: Paul Beard
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Patent number: 7231485Abstract: A mass storage device motherboard or secondary board includes a bridging circuit. The bridging circuit converts signals from the mass storage device into USB signals. The bridging circuit can be provided by a chip that converts ATA/ATAPI signals into USB signals.Type: GrantFiled: November 16, 2001Date of Patent: June 12, 2007Assignee: Cypress Semiconductor Corp.Inventors: David H. Harris, Gordon R. Clark, Stephen D. Holland
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Patent number: 7231374Abstract: An embodiment of a method of evaluating costs and/or benefits of possible configurations of a manufactured product (e.g., an integrated circuit, an electronic system, etc.) includes establishing an upgrade cost and a redesign cost for each characteristic within a set of characteristics associated with the product configuration. The upgrade cost is the cost to upgrade the characteristic in a manner commensurate with other upgraded characteristics, while the redesign cost is the cost to redesign the product to accommodate the characteristic if it is not upgraded commensurately. A predicted total cost and a predicted benefit for a configuration may also be computed. In addition, the total cost for the corresponding configuration may be subtracted from such a benefit to determine a net benefit for the configuration. The method may be implemented using a computer-based system including upgrade cost data and redesign cost data.Type: GrantFiled: May 16, 2000Date of Patent: June 12, 2007Assignee: Cypress Semiconductor Corp.Inventor: Artur P. Balasinski
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Patent number: 7221233Abstract: According to embodiments of the invention, a nonvolatile memory such as a flash memory is used to configure a single die after packaging of the die has occurred. Thus, numerous applications may be supported by a single die or optimization within a given application may occur. According to embodiments of the invention, the nonvolatile memory may be accessed through a programming interface, and preferably, through a two-pin programming interface, to normalize parameters such as package parasitics, crystal variations, output dividers, output duty cycle, output edge rates, I/O configuration, and oscillator gain. According to an embodiment of the invention, an XO circuit configuration includes a nonvolatile memory and a stand-alone XO, where the XO circuit configuration does not require a PLL to synthesize a reference frequency produced by the XO.Type: GrantFiled: September 24, 2004Date of Patent: May 22, 2007Assignee: Cypress Semiconductor Corp.Inventors: Aaron Brennan, Mark Lugar, Mike McMenamy
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Patent number: 7221926Abstract: The present invention a method and apparatus for implementing a short range radio on a single chip. A radio, baseband, and link controller may be fully integrated within a single-chip comprising an area approximately one square centimeter. Through the integration of components upon a single package, cost and real estate savings may be provided in a baseband controller with improved performance.Type: GrantFiled: May 17, 2002Date of Patent: May 22, 2007Assignee: Cypress Semiconductor Corp.Inventor: Paul Beard
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Patent number: 7221200Abstract: A programmable low voltage reset apparatus for a device having a plurality of power supplies comprises a low voltage signal generator for sensing when a power supply output decreases below a predetermined voltage and generating a reset signal, a reset selector for selecting one of the power supplies, and a programmable reference voltage for varying a reference voltage according to the voltage of the selected power supply.Type: GrantFiled: March 8, 2005Date of Patent: May 22, 2007Assignee: Cypress Semiconductor Corp.Inventors: Prasad Kotra, Sunil Thamaran, Shailesh Shah