Abstract: An apparatus for an improved Ball Grid Array (BGA) package includes a semiconductor device having a radio frequency (RF) input or output, an antenna pad, and a BGA package structured to house the semiconductor device and the antenna pad. The antenna pad may be coupled to the radio frequency (RF) input or output, and the antenna pad is structured to reduce the inductance of the BGA package. The antenna pad may include a pad disposed above the semiconductor device, a pad disposed to the side of the semiconductor device, or an antenna chip. An antenna may be coupled to the antenna pad. The antenna may include a trace antenna, a staggered antenna, or a helical antenna.

Abstract: Circuits and methods are provided herein for monitoring the integrity of a power supply, the circuits and methods providing additional resources/information for diagnosing a cause behind a reset signal, and in some cases, a reason behind a power failure. A first method described herein provides exemplary steps for monitoring a level of a power supply voltage supplied to one or more system components. A second method describes exemplary steps for monitoring an electrical connection between the power supply (or ground supply) and one or more supply pins. Each of the methods involves monitoring a state of one or more bits stored, e.g., within a status register. The methods may be used separately, or in conjunction with one another, for detecting the occurrence of a power abnormality.

Abstract: A semiconductor topography is provided which includes a silicon dioxide layer with a thickness equal to or less than approximately 10 angstroms and a silicon nitride layer arranged upon the silicon dioxide layer. In addition, a method is provided which includes growing an oxide film upon a semiconductor topography in the presence of an ozonated substance and depositing a silicon nitride film upon the oxide film. In some embodiments, the method may include growing the oxide film in a first chamber at a first temperature and transferring the semiconductor topography from the first chamber to a second chamber while the semiconductor topography is exposed to a substantially similar temperature as the first temperature. In either embodiment, the method may be used to form a semiconductor device including an oxide-nitride gate dielectric having an electrical equivalent oxide gate dielectric thickness of less than approximately 20 angstroms.

Abstract: Systems and methods of flyback capacitor level shifter feedback regulation for negative pumps. In accordance with a first embodiment of the present invention, a feedback regulator for a negative output charge pump comprises a flyback capacitor for inverting an output of the negative output charge pump to a positive voltage. The feedback regulator further comprises a voltage comparator for comparing the positive voltage to a reference voltage. The voltage comparator is also for producing an enable signal for control of pump driving signals to the negative output charge pump. The feedback regulator further comprises a first plurality of switches for selectively coupling a first terminal of the flyback capacitor between a low voltage and the output and a second plurality of switches for selectively coupling a second terminal of the flyback capacitor between a low voltage and the voltage comparator. Further, the feedback regulator comprises switch control logic for controlling the plurality of switches.

Abstract: A switch circuit, system, and method are provided in which a single, shared data line is formed across the majority of the monolithic substrate which bears the switch. The shared data line is serviced by multiplexers and corresponding state machines placed near the ports of the switch. The state machine determines which one of a plurality of data streams received on the corresponding ports are to be serviced and placed in a first timeslot of multiple timeslots sent across the shared data path. A multiplexer select input responds to the state machine output by forwarding the selected data stream for a duration set by a timer within the state machine. An arbiter within the corresponding state machine determines which port is to served first and which data is to be placed in the first timeslot, but also can prioritize based on user-defined rules.

Abstract: A data interface is provided that can de-skew data signals by taking into account different skewing effects on each data signal. The data interface can be used, for example, in a communication system and can be configured to operate in one of three possible modes of operation. In the first mode, de-skewing is fixed prior to the sample logic. In the second mode, de-skewing is periodically changed automatically as the amount of skew changes based on training signals that are periodically sent into the data interface. The combination of the data phase count and the positive and negative clock width pulse counts will then determine where the final transition or edge of each data signal is to be placed within a bit. The third mode of operation involves an override or programmatic modification of the second mode of operation based on values stored in a register.

Abstract: A method and apparatus for creating USB peripheral device report descriptors: A short, compressed, report descriptor is stored in a peripheral device. This short report descriptor is transmitted to a USB wireless bridge and combined with templates stored in the bridge to create a USP report descriptor. Power is saved because less time is required to transmit the short report descriptor than would be required to transmit a full USB report descriptor. Hardware is also saved in the peripheral device since less memory is required to store the short report descriptors as compared to storing a full USB report descriptor.

Abstract: An oscillator amplifier circuit is provided. The amplifier circuit can be used with a resonator to amplify and form a resonating oscillator. The amplifier circuit comprises an active circuit which includes an inverter and a current-controlled biasing circuit. One transistor of the inverter receives a voltage produced from the biasing circuit in order to place a gate terminal of that transistor at approximately a threshold voltage. The other transistor can be biased using a passive circuit element, such as a resistor. Therefore, both transistors are biased independent of each other within the optimal gain region. Large shunt capacitors are not required and the total current consumption is controlled through a variable resistor coupled to the source terminal of either the first transistor, second transistor, or possibly both transistors of the inverter to adjust the amplitude of the oscillating output.

Abstract: A method for arranging a semiconductor wafer within a photolithography tool and methods for processing a semiconductor wafer employing such an arrangement process are provided. The arrangement process includes positioning a semiconductor wafer on a stage in a pre-alignment unit of a photolithography tool such that a crystal orientation marker of the wafer is located at a first radial position. Thereafter, the wafer is moved to an exposure unit of the photolithography tool. During one or both of such steps, the semiconductor wafer is rotated such that the crystal orientation marker is relocated to a second, distinct radial position prior to arranging the wafer upon a stage of the exposure unit. In particular, the semiconductor wafer is rotated greater than approximately 10° and less than approximately 170° relative to the first radial position. The arrangement process is performed for lithography processes conducted during fabrication of a semiconductor device.

Abstract: A low voltage detect circuit is provided herein for detecting when an external voltage (Vext) drops below a predetermined minimum voltage. In general, the low voltage detect circuit described herein may be configured to detect a low voltage condition based on a threshold voltage difference between a non-zero threshold transistor having a substantially non-zero threshold voltage, and a zero threshold transistor having a threshold voltage relatively close to zero. According to a particularly advantageous aspect of the invention, the low voltage detect circuit described herein comprises substantially no resistors or reference voltage generation circuits, and therefore, provides significant savings in both current and die area consumption without sacrificing accuracy. The low voltage detect circuit of the present invention is particularly useful in power regulators, such as those used in memory systems or devices.

Abstract: An apparatus, computer program, and method are disclosed for generating computer executable code. The code is compiled from a data set, and the data set is compiled by selecting a link within a comments portion of a text editor portion of a program. The data set can then be inserted into an applications program to form the computer executable code. The comments portion involves a line of text that is preceded by a comments designator and succeeded by at least one link word that is adapted for modification by an on-screen pointer. Any changes to the link word via a graphical user interface will correspondingly change fields within a data set, which preferably is also displayed within the same window as the comments portion. The fields of bits within the data set can be used to program a hardware device or system. One example of such a device is a programmable device, or general purpose interface circuit that is juxtaposed between, for example, a computer and a peripheral device.

Abstract: Embodiments of the invention include a bus bridge that is capable of communicating with more than one MSC device coupled to it. In some embodiments, the bridge includes a LUN processor that translates different LUN numbers received from the bus into different addresses and LUNs for devices connected to the bridge. The bridge masks the fact that multiple MSC devices are coupled to it by reporting to the host that only a single device having multiple LUNs are coupled to the bridge.

Abstract: A disclosed circuit includes circuitry for coupling to a volatile memory, circuitry for coupling to a nonvolatile NAND flash memory, and circuitry that: (i) receives a volatile memory request from a processor and satisfies the volatile memory request by accessing the volatile memory, and (ii) receives a nonvolatile NOR flash memory read request from the processor and satisfies the NOR read request by accessing both the NAND flash memory and the volatile memory. The circuit may also include circuitry that receives a volatile memory request from another processor and satisfies the volatile memory request from the other processor by accessing the volatile memory, and circuitry that receives a NAND flash memory read request from the other processor and satisfies the NAND read request by accessing the NAND flash memory. Multiprocessor systems including the circuit are described, as is a method for satisfying a NOR flash memory read request.

Abstract: An address transition detector (ATD) system is provided with an integrator, a feedback circuit and an output circuit. The integrator has an enhanced architecture that ensures a fast output signal switching, low power consumption during the integration time, fast output transition at the end of the integration time and compensates the delay variations over process, voltage and temperature (PVT) fluctuations. The ATD system can be used in any asynchronous memory. In addition, the ATD integrator can be employed as a standalone circuit for use whenever a signal transition is to be delayed.

Abstract: A method for reducing the surface roughness of a metal layer is provided. In some embodiments, the method may include polishing the metal layer to a level substantially above any layers arranged directly beneath the metal layer. In some cases, the semiconductor topography comprising the metal layer may be substantially absent of any material laterally adjacent to the metal layer during polishing. In either case, a semiconductor topography having a metal layer with a mean surface roughness less than the mean surface roughness obtained during the deposition of the metal layer may be obtained. As such, the method may include reducing the mean surface roughness of a metal layer. For example, the method may include reducing the mean surface roughness of a metal layer by at least a factor of ten.

Abstract: A system and method for bi-directional communication between a system controller and a fan controller: The system operates in two modes and there are two communication paths between the system controller and the fan controller. The first communication path provides a PWM signal the frequency of which indicates the mode in which the system is operating. During the first mode, the duty cycle of the PWM signal on the first signal path indicates the desired fan speed. In the first mode, the second communication path carries a conventional tachometer signal. In the second mode the second communication path operates as a bi-directional communications signal path between said system controller and said fan controller.

Abstract: According to one embodiment, a phase-locked loop (PLL) device includes test circuitry for entering/exiting a test mode upon receiving a particular pulse train at a reference clock input of the PLL. In addition, exemplary methods are provided herein for entering a test mode and detecting loop filter leakage within the PLL. The methods described herein are performed without the use of a dedicated test pin.

Abstract: A test circuit, system, and method are provided herein for testing one or more circuit components arranged upon a monolithic substrate. According to one embodiment, the system may include a test circuit and one or more circuit components, all of which are arranged upon the same monolithic substrate. In general, the test circuit may be configured for: (i) receiving an input signal at an input frequency, (ii) generating a test signal by modulating a phase of the input signal in accordance with a periodic signal, and (iii) supplying either the input signal or the test signal to the one or more integrated circuits, based on a control signal supplied to the test circuit. More specifically, the test circuit may be used to determine the jitter and/or duty cycle distortion (DCD) tolerance of any system component without changing the frequency of the clock signal supplied to the component or injecting noise into the clock recovery system.

Abstract: An improved ESD protection device, integrated circuit and method for programmably altering a sensitivity of the ESD protection device is provided herein. More specifically, an active shunt ESD protection device is provided with an improved trigger circuit design. The improved trigger circuit design enables the sensitivity of the ESD protection device to be altered by providing a variety of programmable elements for adjusting an RC time constant of a slew rate detector contained therein. The programmable elements allow the RC time constant to be altered at the wafer or package level, and avoid the significant time and cost typically associated with conventional trial-and-error adjustment procedures.

Abstract: A system and method are provided herein for monitoring the integrity of a power supply by monitoring a level of the power supply voltage supplied to one or more system components. The method, as described herein, includes setting a bit in a status register after the power supply level reaches a threshold level, and monitoring a state of the bit to determine if the power supply level has dropped below the threshold level. For example, the method may determine that the power supply level has dropped below the threshold level if the state of the bit changes from a set bit to a cleared bit. In addition, the system and method described herein may be used for detecting the occurrence of a power abnormality by providing additional resources/information about a power related event.