Abstract: A method of manufacturing an integrated circuit having a multilayer structure where the method includes the steps of depositing a thin layer of low temperature oxide (LTO) on top of conductors and then spinning and curing a thin layer of spin-on-glass to planarize the surface of the device. This structure is then plasma etched to remove the spin-on-glass and a portion of the LTO at approximately the same rate. The structure is then dipped in a mild potassium hydroxide solution to completely remove the SOG material, even from the crevices and gaps which are present on the surface. This enables the device to be manufactured free of any organic substances from the SOG in the body of the structure. A passivation layer can now be deposited to protect the underlying circuitry from ionic contamination, water vapor penetration and handling.

Abstract: A circuit for compensating for MOS device response to supply voltage variations, as well as temperature and process variations, in an integrated circuit device. The compensation circuit produces a reference voltage which modulates the gate bias voltage of a MOS transistor such that the gate-to-source bias of the MOS transistor is varied to compensate for variations in the supply voltage as well as for variations in the temperature and manufacturing process. The circuit pulls up the reference voltage toward the supply voltage as the supply increases, thereby increasing the gate drive on the MOS transistor. The circuit provides compensation for both AC and DC supply variations. The MOS transistor is used to modulate the available current sinking capability in an IC device output buffer, such that as the MOS gate drive increases, the current sinking capability is reduced, thereby slowing the output state transitions as the supply increases, and reducing noise caused by supply variations.

Abstract: Programmable high speed state machines with sequencing capabilities based on a dual array structure with state information and fast sequencing logic placed between the two arrays are disclosed. The state section consists of multiple registered macrocells which are connected to function as program counters and decoders to the output array. The input array has feedback from the state registers and input from the dedicated inputs and input/output pins around the device. The inputs of the input array are all individually configurable as registered or nonregistered, with the inputs being divided into three groups, input/output, Mealy and simple inputs, with three enable product terms from the output array controlling the respective groups. Various additional characteristics, features and capabilities of the invention are disclosed.

Abstract: A power reduction circuit for selectively providing power to circuitry associated with and coupled to the power reduction circuit, which includes two transistors having current paths coupled in parallel and a nonvolatile programmable storage device having a current path coupled in series with the current paths of the two transistors. A control transistor which is also part of the power reduction circuit includes a current path between a power supply and the circuitry associated with and coupled to the power reduction circuit to selectively provide power to the associated circuitry. The control transistor has a control gate electrode which is coupled between the current path of the nonvolatile programmable storage device and the current paths of the two transistors. The state of the storage device controls the state of the control gate electrode of the control transistor and accordingly controls whether the power is supplied to the associated circuitry.

Abstract: Apparatus for controlling the programming voltage of an EPROM array composed of a plurality of programmable floating gate MOS cells, which includes an additional floating gate MOS cell fabricated on the same chip and in the same manner as the array of cells, the additional cell not being connected for programming during the normal programming of the array. A voltage is applied to the additional cell to generate a drain current through the cell. A feedback control is connected between the source of external programming voltage for the array and the actual voltage within the array used for programming the cells, the feedback control using the amplitude of the drain current in the additional cell to control the magnitude of the actual programming voltage in the array in such a manner that when the drain current of the additional cell increases, the programming voltage decreases proportionately.

Abstract: The invention relates to an improved CMOS clamped sense amplifier having an input terminal adapted to receive the signal to be sensed. The signal passes through a CMOS input clamp circuit which includes a pair of complementary MOS transistors having their drains coupled together and to the input terminal, and their sources adapted to be coupled respectively to opposite power supply terminals. The input signal also passes to a voltage gain stage coupled to the input terminal and having an output terminal for providing the amplified output signal from the sense amplifier. To achieve the enhanced signal throughput speed, a resistance means is employed, coupled between the gates of the transistors of the CMOS input clamp circuit and the input terminal. Although this resistance reduces the clamping effectiveness of the clamping circuit, it still decreases the overall throughput time through the sense amplifier, thus increasing switching speed.

Abstract: A Bi-CMOS ECL semiconductor memory cell having a read word line, a write word line and a read bit line is disclosed. The cell includes a bistable circuit having complimentary outputs and also includes a first transfer device and a second transfer device, each having a gate electrode and a current path, the gate electrode of one transfer device being coupled to one of the complimentary outputs of the bistable circuit and the gate of the other transfer device being coupled to the other complimentary output, and the two current paths of the two transfer devices being coupled in series between the read word line and a first reference voltage. The cell further includes a bipolar transistor device having a base, a collector and an emitter.

Abstract: The invention relates to a random access memory having more than one port capable of accessing the same storage addresses. It provides a system for protection of data integrity at each port. First and second ports are capable of providing first and second address transition signals to enable data storage in a single memory address. A comparator is coupled to the first and second ports (1) for detecting address transitions indicating that the second port is addressing a particular memory address coincidentally when the first port also is addressing the same memory address, and (2) for generating a busy output signal for that address in the event of such coincidence. A transition detection circuit is used to detect the transition resulting from the removal of the busy output signal from the comparator and for providing a busy removal output signal equivalent to an address detection signal in the event of such detection.

Abstract: A first-in first-out buffer memory with improved status flags to indicate not only memory empty and memory full conditions, but to further indicate conditions such as almost empty, almost full and half-full is disclosed. To generate the flags, counters continuously count the number of write and read operations, with a subtractor coupled thereto providing as an output the difference between the two counts. Time delay circuits initiated by write or read operations provide time delays sufficient to enable the counters and the subtractor to settle before clocking the result into a latch. The output of the latch is decoded, with a further time delay circuit clocking the decoder output thereinto to provide output signals for the foregoing status flags. The use of the time delay circuits and the clocking of status flags avoids any significant flag invalid time, making the flag signals constantly monitorable without regard to the timing of read and write operations.

Abstract: An improved architecture for and a method of operating a high speed synchronous state machine is disclosed having a programmable logic array receiving inputs from dedicated input registers and having an input/output macrocell which includes two state registers and two input registers, and two transparent latches and two feedback multiplexers. The outputs from the input registers are multiplexed through an input multiplexer and the input registers may be clocked at different input clock rates than the state clock which clocks the state registers.

Abstract: The invention pertains to an output buffer circuit capable of switching from the off state to the on state, and from the on state to the off state, without generating significant noise. The circuit includes an MOS inverter circuit having a first node adapted to be connected to one terminal of a power supply and a second node adapted to be connected to the other node, and having an input for receiving an input signal and an output for providing an output signal adapted to be connected to an output transistor. The circuit also has a first MOS transistor of one polarity type and one mode having its source-drain circuit coupled in series with the first node of the inverter circuit, and a second MOS transistor opposite in either polarity type or mode from the first MOS transistor, having its source-drain circuit coupled in series with the other node of the inverter circuit.

Abstract: A fast EPROM programmable logic array cell utilizing a MOSFET to drive the output of the EPROM array cell which is coupled to a product term. The MOSFET has a current path which is coupled to the product term to modulate the binary status of the product term under control of an MOS EPROM field effect transistor which is coupled to the MOSFET. The MOSFET is other than an EPROM field effect transistor.

Abstract: The invention pertains to a circuit for controlling the power to a plurality of sense amplifiers used for sensing data on data lines in an array of floating gate storage cells, wherein the data stored in the array is sensed at regular intervals. The circuit includes a first plurality of data paths through the array, and a second data path containing replications of all necessary circuit elements in the first plurality of data paths to assure that the data delay through the second path equals or exceeds the maximum delay in any of the first plurality of data paths. A clock is used to provide an initiation signal which starts the propagation of input data through the array. A means is coupled to the clock for sending a dummy data pulse through the second data path upon receipt of the initiation signal, and a detecting means detects the completion of the passage of the dummy data through the second path and supplies a completion signal in response.

Abstract: A semiconductor memory for storing binary data which may be accessed more rapidly is disclosed which semiconductor memory includes a pair of differential bit lines for receiving signals corresponding to the binary data; a semiconductor memory device for storing binary data is coupled between the differential bit lines to provide signals corresponding to the binary data when reading the semiconductor memory device during the read cycle. A semiconductor clamping device is coupled between the differential bit lines to selectively provide a current path between the differential bit lines during the reading of the semiconductor device.

Abstract: An input buffer for coupling TTL logic circuits to CMOS logic circuits, the buffer being used to convert between standard TTL logic signals and CMOS logic signals. The buffer includes a first inverter circuit and a second inverter circuit coupled in a cascade (output of first inverter coupled to the input of the second inverter). The first inverter includes two resistors (Rcc and Rss); the Rcc resistor couples the first inverter to a first reference voltage, which is usually a power supply voltage rail, and Rss couples the first inverter to a second reference voltage. The first inverter also includes a capacitor coupled in parallel with that inverter. Power supply noise is isolated from the first inverter so that the buffer has better immunity from noise than the prior art.

Abstract: A process for minimizing bird's beak in local oxidation of silicon which is compatible with high density (VLSI) semiconductor devices is disclosed. A pad oxide is nitridized using rapid thermal nitridization, which works quickly with minimal thermal cycling of the wafer. A silicon nitride film is then deposited over the nitridized oxide. Both films are exposed to dry plasma etching which gives more consistent results than wet methods. The field oxide is then grown and finally the masking films of the nitridized oxide and silicon nitride are removed, whereby field oxides are grown with minimal bird's beak, and minimal damage to the wafer with a small number of steps. The pad oxide may be grown in the same rapid thermal annealer used for the rapid thermal nitridization. Both cycles (pad oxide growth and nitridization of the pad oxide) can be integrated to "one" cycle and performed sequentially in the same rapid thermal annealer to increase throughput and improve device quality.

Abstract: A reference circuit for compensating for the natural response of MOS circuits to changes in temperature and manufacturing variances. The reference circuit comprises a voltage reference circuit that generates a stable current over variations of temperature and includes a current mirror circuit coupled to a first MOS transistor which is biased so that its change in threshold voltage due to temperature variations is compensated by its change in transconductance due to temperature variations, which voltage reference circuit produces a stable current through a second MOS transistor, which stable current is applied to a voltage generator circuit which modulates the gate bias voltage of a third MOS transistor such that the gate to source bias of the third MOS transistor is varied to compensate for variations in temperature.

Abstract: A CMOS semiconductor device which avoids latchup in the powerup mode as well as in the normal operating mode is provided. The device is provided with an on-chip back bias generator which greatly reduces the possibility of forward biasing parasitic NPNP transistors in normal operation. During the powerup mode, before the backbias voltage becomes effective, a clamp diode provided in integrated form outside a guardring surrounding the circuit elements is effective to clamp a large negative voltage that may be created by a "hot-socket" connection to an output. In a modified form of the invention, a junction field effect transistor is provided to prevent forward biasing of the parasitic transistors in a somewhat different manner.

Abstract: A current limiting, process compensating circuit for CMOS memory arrays is provided. A dual transistor bias circuit is connected to each of a pair of columns of the array with a four transistor voltage reference circuit having its output connected to the gates of the active P-channel transistor of each bias circuit. A first P-channel transistor of the voltage reference circuit is sized to be less than the P-channel transistor of the bias circuit and the other three N-channel transistors are sized to be the same as the second transistor of the bias circuit and the two transistors of each memory cell in the array. As supply voltage to the array moves up or down making more or less current available, the combined circuit maintains nearly constant current on the first transistor of each bias circuit while compensating for process variation.