Abstract: A memory includes a memory array and a decoder. The memory array includes a plurality of memory locations and the decoder is coupled to receive an address for decoding the address to generate a select signal for selecting one of the plurality of memory locations in the memory array for a memory operation. The memory further includes circuitry coupled to the decoder for delaying the select signal for a first predetermined delay time to generate a delayed select signal and for selectively applying one of the select signal and the delayed select signal to the memory array. The circuitry applies the delayed select signal to the memory array during the memory operation before the select signal is to be deasserted such that address hold time of the memory operation is decreased without affecting the memory operation.

Abstract: An apparatus and method for implementing flexible redundancy memory block elements in a divided array architecture scheme. The apparatus comprising the plurality of memory sub-arrays. Each of the memory sub-arrays includes a plurality of memory blocks having unique addresses and at least one redundancy memory block having a programmable element. Each of the memory sub-arrays is coupled to a plurality of global wordlines which are not uniquely addressed. The memory sub-arrays, namely the memory and redundancy memory blocks, are coupled to a true global read bus to allow the redundancy memory in one memory sub-array to be shared by another sub-array. The method comprises the steps needed to practice the present invention.

Abstract: A computer memory system incorporates a gang write circuit block to reduce the number of clock cycles required write a background pattern to memory cells during a memory test operation. The computer memory system includes (1) a two-dimensional array having multiple memory cells arranged in M rows and N columns and (2) the gang write circuit block for writing to N memory cells located in a row during one cycle and for writing to all of the memory cells in M cycles. The gang write circuit block may include two inverters for each column of the memory array and two test signals for the inverters. The background pattern may be all 1's, all 0's or some combination of 1's and 0's. The gang write circuit block becomes inactive during a normal read and write operation. When all the word lines of the computer memory system are selected, all the memory cells are written simultaneously.

Abstract: An ESD protection structure for p-well technology using nMOS FETs that prevents the lock-on condition normally occurring after one FET of a multi finger structure snaps back. The multifinger structure is contained in a main p-well and channels ESDs of a first polarity from the contact pad to a metal conduit. A resistance is provided between the main p-well and the conduit. Further, the circuit channeling ESDs of a polarity opposite to the first polarity is contained in a second p-well that is distinct from the main p-well. An ESD event causes one of the fingers to snap back. Resulting drain current through that finger generates electron hole pairs in the main p-well by impact ionization. Thus generated holes, traveling to the conduit through the resistance, raise the voltage of the main p-well, and therefore shift the i-v characteristic curves of all the FETs to a point where they no longer exhibit a knee.

Abstract: A novel, high-performance BiCMOS Output Driver. The Output Driver comprises a first pull-up means for pulling high the output of the Output Driver and a pull-down means for pulling low the output of the Output Driver. The first pull-up means includes a bipolar transistor. Coupled in parallel with the first pull-up means is a MOS transistor wherein the gate of the MOS transistor is electrically isolated from the base of the bipolar transistor.

Abstract: A nonvolatile memory circuit having a decoding scheme for reliable multiple bit hot electron programming. The nonvolatile memory circuit has a memory array in which data received at each data input can be programmed into multiple memory bits simultaneously. The address of each memory bit selected for programming is decoded by a row decoder and a column decoder. The row decoder decodes the word line of each selected memory bit and the column decoder decodes the bit line of each selected memory bit. The column decoder includes a programming column decoder and a read column decoder. The programming column decoder is enabled during a programming operation and disabled during a reading operation. The read column decoder is enabled during a reading operation and disabled during a programming operation. During a programming operation, a programming voltage is applied to the nonvolatile memory.

Abstract: A method of etching openings in oxide layers is disclosed. A hard mask layer is formed on the oxide layer. The hard mask layer is then patterned by a photoresist layer and an etch is performed to form openings in the hard mask. Next, the patterning layer may be removed and an etch is performed to remove the oxide in the regions defined by the hard mask layer openings. The etch with hard mask has minimized aspect ratio dependency, so that openings of different sizes may be formed simultaneously. An etch that may be carried out with Freon 134a (C.sub.2 H.sub.2 F.sub.4) to provide superior oxide:nitride selectivity is also disclosed. Additionally, the etch may be carried out at high temperature for improved wall profile without loss of selectivity. For deep openings, a two step etch process is disclosed, with a polymer clean step between the etches to remove polymer build up from first etch, and allow the etch to proceed to an increased depth.

Abstract: An OR array including a first multiplicity of OR devices, to which a second multiplicity of product term signals are variably distributed. Some product term signals are distributed to four OR devices, other product term signals are distributed two or three OR devices, and still other product term signals are distributed to only one OR device.

Abstract: A phase detector is described. The phase detector receives a data signal from an external circuit. The phase detector generates a first signal when a transition edge of the dock signal occurs after a transition edge of the data signal. The phase detector generates a second signal when the transition edge of the dock signal occurs before the transition edge of the data signal and generates a third signal when the data signal remains in a same signal state for at least two transition edges of a same type of the dock signal.

Abstract: The burst mode memory architecture using interleaved memory arrays provides even and odd EPROM arrays with data having even addresses stored in the even array and data having odd addresses stored in the odd array. A control circuit receives an initial address from a memory system controller and then accesses all data from the even and odd arrays within a burst address space containing the initial address. A pair of out-of-phase counters generate even and odd addresses, respectively, for accessing the even and odd arrays. Each counter increments addresses sequentially until a burst address space boundary is reached, then the counters wrap around to a beginning of a burst address space to generate any remaining addresses within a burst address space. The burst mode control circuitry is capable of processing a variety of burst sequencing modes. The burst address space size and the burst sequencing mode are selectable.

Abstract: Static random access memory cells (SRAMS) containing five MOS transistors are configured in a memory array such that only three bitlines are required for two cells. A first bitline is coupled to a first side of a first memory cell, and a second bitline is coupled to a first side of the second memory cell. The first and second memory cells share either a common power bitline or a common ground bitline. A control circuit executes a special write operation to write a low logic level on the second side of the memory cells. The control circuit is coupled to the first, second, and third bitlines to generate a first differential voltage across the memory cells that is lower than the operating voltage on the third bitline and to generate a second voltage lower than the operating voltage on the second bitline when storing a low logic level on the second side of the first storage cell.

Abstract: A method and apparatus are disclosed for writing to a large content addressable memory (CAM) array without causing substantial power supply current surges, for providing fully static CMOS memory cells, for providing a consistent precharge of bit and bit bar lines, for providing a column write capability, and for increasing a read current while reducing a read disturbance probability. Each memory cell in the CAM array has (a) a data write circuit for accepting data, (b) a latch circuit for latching the data in the memory cell, (c) a hold circuit to allow holding the data or writing new data, (d) a data compare circuit for comparing the new data to the stored data, and (e) a data read circuit for reading the stored data.

Abstract: A programmable crystal oscillator that generates a wide range of possible frequencies with high stability is disclosed. The programmable crystal clock oscillator includes an industry standard oscillator package, a programmable storage, a crystal and a phase lock loop (PLL) circuit coupled to the crystal and the programmable storage. The industry standard package does not contain any dedicated programming connections. A programmable storage, contained within the package, stores parameters representing a desired output frequency for the crystal oscillator. The crystal is enclosed within the package and provides a source frequency. The PLL circuit, also enclosed in the package, receives the source frequency, and produces the desired output frequency, within the wide range of possible frequencies, based on the parameters.

Abstract: A method of forming a chlorinated silicon nitride barrier layer is disclosed. The method of the present invention includes depositing a silicon nitride layer over a semiconductor substrate. The silicon nitride layer is exposed to an ambient including chlorine at an elevated temperature for a predetermined time to form the chlorinated silicon nitride barrier layer that is resistant to attack by at least one reactive compound.

Abstract: A method for forming a stable plasma, particularly in the high power and low pressure ranges. The method may be used in a plasma system such as that used for a plasma etch. First, the radio frequency power is turned on under low power and high pressure. The plasma is allowed to stabilize without tuning. Next, the pressure is dropped to the desired operating level and the tuning system is engaged. After tuning at the low power and low pressure, the radio frequency power is ramped to the desired level. Finally, the system is again tuned at the higher power.

Abstract: A method is described for eliminating overerasure in a nonvolatile memory that includes a plurality of memory cells, each having a control gate, a floating gate, a drain, and a source. The nonvolatile memory is electrically erased until each of the plurality of memory cells has a threshold voltage below a predetermined erased voltage state. The nonvolatile memory then undergoes an equalization programming operation by applying an equalization programming voltage to the control gate of each of the plurality of memory cells such that the threshold voltage of each of the plurality of memory cells is saturated to the predetermined erased voltage state. The equalization programming voltage determines the predetermined erased voltage state. An apparatus for eliminating overerasure in the nonvolatile memory during erasing is also described.

Abstract: A method for forming an alignment mark during semiconductor device manufacturing. A first area and a second area are provided on the semiconductor substrate wherein the second area is adjacent to the first area. An alignment mark is formed in the first area. A first layer is formed over the first area and the second area wherein the alignment mark is replicated in the first layer. The first layer is then removed from the second area and left over the first area. A globally planarized second layer, is formed over the first area and the second area. The second layer is then removed from the first area and is left over the second area.

Abstract: An adaptive active filtering method and apparatus that detects changes in noise conditions and reduces the signal propagation speed as noise conditions worsen. This active filter has a level shifting inverter, which inverts the input signal and converts the logic levels of the input signal into chip logic levels. This inverted input signal is presented at the input of a driver inverter, which once again inverts the signal. This second inversion filters out input noise, because a voltage controlled device (which is attached to the driver inverter) reduces the switching speed of this inverter as the noise condition worsen; this reduction in switching speed reduces the propagation speed and thus filters out noise.

Abstract: A non-volatile memory device is described. The memory device includes a memory array and current regulating circuitry coupled to the memory array. The memory array includes a first memory cell coupled to a first bit line and a second memory cell coupled to a second bit line such that the first memory cell receives a first current during programming of the first memory cell and the second memory cell receives a second current during programming of the second memory cell. The current regulating circuitry regulates the first and second currents during programming of the first and second memory cells such that when the first cell is being programmed and the second cell is not being programmed, the circuitry limits the first current flowing through the first bit line for programming the first memory cell to be substantially equivalent to the first current if the first and second memory cells are being programmed substantially at the same time.

Abstract: A logic circuit implementing a logic NAND function with respect to a first input signal and a second input signal is described. First and second P-channel transistors are coupled in parallel to a power supply and an output node. Each of the first and second P-channel transistors receives the respective one of the first and second input signals. A first circuit branch has a first and a second N-channel transistor. The first N-channel transistor has a first end coupled to the output node and a second end coupled to a first end of the second N-channel transistor. The second N-channel transistor has a second end coupled to ground. The first N-channel transistor receives the first input signal and the second N-channel transistor receives the second input signal. A second circuit branch has a third and a fourth N-channel transistor. The third N-channel transistor has a first end coupled to the output node and a second end coupled to a first end of the fourth N-channel transistor.