Abstract: A fast, fieldless flash memory cell includes an erase node having a control gate and a floating gate, both formed of polycrystalline silicon, a program transistor sharing the floating gate and control gate with the erase node, and a read transistor sharing the floating gate and control gate with the erase node and program transistor. The inventive memory cell is suitable for use in fast Programmable Logic Devices (PLDs) in the sub 5 nS range (2-5 nS), and other logic and memory parts.

Abstract: An associative processing memory system for concurrent data searching or processing includes a content addressable memory (CAM) array, a general register block, an interface register logic block, and a general control block. The CAM array is accessed for read or write by a select vector generated by the general register logic block. The select vector is selected through a multiplexer from at least four sources: the match latch, the multiple response resolver, the general purpose logic block and a supplies one unit. The interface register logic block provides input/output data registers, mask register, command register, and control/status register. The general control block generates control signals to the CAM system in response to bus signals. The match operation for the CAM array can be performed on all words in a single operation. A set of CAM instructions is used to control CAM operations including data movement, shifting, read/write, and match.

Abstract: A method for forming an alignment mark during semiconductor device manufacturing. A first area and a second area are provided on the semiconductor substrate wherein the second area is adjacent to the first area. An alignment mark is formed in the first area. A first layer is formed over the first area and the second area wherein the alignment mark is replicated in the first layer. The first layer is then removed from the second area and left over the first area. A globally planarized second layer, is formed over the first area and the second area. The second layer is then removed from the first area and is left over the second area.

Abstract: A phase detector detects a transition edge on a received data signal and generates a pump-down reference pulse and a pump-up, variable width pulse indicative of phase to synchronize a local clock with the received data signal. The variable width pulse overlaps in time with the reference pulse. The reference pulse is subtracted from the variable width pulse, and the resulting difference signal is supplied in an integrated format to a voltage controlled oscillator (VCO) that controls the frequency of the local clock. When the phase detector is balanced, the variable width pulse and the reference pulse substantially cancel out one another, providing for relatively reduced jitter for the local clock.

Abstract: An improved sense amplifier for receiving differential inputs and providing an output signal. A level shifting circuit for receiving differential inputs (IN and IN) is provided. A pre-amplification circuit that is coupled to the level shifting circuit provides gain to the differential outputs. A first inverter is coupled to the pre-amplification circuit and provides high voltage gain to the output signal. The first inverter includes a power port for receiving a power voltage signal and a ground port for receiving a ground signal. A second inverter that has a ground port and a power port is coupled to the pre-amplification circuit. The power port of the first and second inverters are coupled to the power voltage supply through a first transistor. Similarly, the ground port of the first and second inverters are coupled to the ground via a second transistor. The output of the second inverter is coupled to the gate of the first and second transistors and controls the first and second transistors.

Abstract: A method and apparatus for generating an asynchronously clocked signal in a synchronously clocked programmable device is described. A programmable logic device having synchronously clocked or product term clocked registers receives an input signal and an event signal. The input signal and the event signal can be any externally or internally generated signals. The event signal signifies the occurrence of a particular event by transitioning from one signal state to another. The input signal is asynchronously clocked through the synchronously clocked PLD without utilizing the synchronously clocked or product term clocked registers. The input signal is asynchronously clocked in response to an edge transition of the event signal. The edge transition of the event signal being either a failing edge or a rising edge.

Abstract: A pseudo-differential sense amplifier with improved common mode noise rejection is disclosed. The sense amplifier is connected to a memory cell via an array path and generates an output signal indicative of the state of the memory cell. The sense amplifier includes an array load device connected via an array node to the array path, a reference load device connected via a reference node to a reference path, a differential stage having a first input connected to the reference node, a second input connected to the array node and an output generating the output signal. The sense amplifier further includes a balancing device, connected to the reference node, for compensating a change in signal, caused by a noise event, at the array node and, thus reducing a delay in the response of the sense amplifier when a transition in the state of the cell occurs.

Abstract: The present invention provides an EPROM bit-line interface with multiple functions. The invention is constructed by combining a bit/sense amplifier with two transparent latches operating on opposite edges of a timing clock. The two transparent latches form a latch and a register for holding the contents of the EPROM during power down. A bit driver is enabled when it is desirable to program the EPROM. The first transparent latch captures the contents of the EPROM when the EPROM is powered down. The first transparent latch also forms the first half of a register for shifting the contents of the EPROM to an external device. The first transparent latch operates on the leading edge of a timing clock. The second transparent latch operates on the trailing edge of a timing clock. By combining two transparent latches in series, a shift register is implemented. The shift register is used to hold the programming information while the EPROM is programmed.

Abstract: A high-speed programmable macrocell includes structure sufficient to implement a combined in the combinatorial storage signal path when the macrocell is operated in the combinatorial, and storage modes of operation. The macrocell includes, a master circuit (including a polarity multiplexer), and a slave circuit (including a transmission gate). The polarity multiplexer is responsive to input data for generating an output signal corresponding to one of a true and complemented state of the input data, according to a polarity configuration bit. The master circuit stores the multiplexer output in response to a low-to-high transition of a clock signal when operating in the storage mode. The master circuit, when in the combinatorial mode, will always pass the multiplexer output therethrough.

Abstract: A method of forming a multi-layer silicide gate structure for a MOS type semiconductor device that includes the processing steps of first providing a substrate, then depositing a gate oxide layer on the substrate, then depositing a first refractory metal silicide layer which has a first stoichometry on the gate oxide layer, and finally depositing a second refractory metal silicide layer which has a second stoichometry different than the first stoichometry on the first deposited refractory metal silicide layer.

Abstract: The invention describes an asynchronous state machine with a programmable tSKEW that is used to generate an empty and full flag in a synchronous FIFO buffer. The present invention reduces the delay associated in producing the full or empty flags from a typical eight gate delays, to as little as no gate delays. The present invention accomplishes this by using a set state machine which can only make an internal flag go low, or active, and a reset state machine which can only make the internal flag go high, or inactive. The functioning of the set state machine and the reset state machine is controlled by a blocking logic. The output of each of the state machines is stored in a latch. The output of the latch is presented to an input of the blocking logic, which is used by the blocking logic to control the activity of the state machines.

Abstract: A protective circuit for protecting internal circuits of semiconductor integrated circuits (ICs) from ElectroStatic Discharges (ESD) into a voltage conduit of a semiconductor IC. The protective circuit is coupled in parallel with the internal circuit of the semiconductor IC such that the protective circuit and the internal circuit are each coupled to a first voltage conduit at a first reference voltage at one end and to a second voltage conduit at a second reference voltage at another end. The protective circuit includes an ESD protection device (or devices) for channeling an ESD discharge from the first voltage conduit through the protective circuit to the second voltage conduit. The protective circuit also includes a control circuit for turning "on" (e.g. operating in a low impedance state) the ESD protection device during the occurrence of the ESD discharge into the first voltage conduit.

Abstract: An integrated circuit device includes internal power supply buses V.sub.SSI, and V.sub.DDI, and output power supply buses V.sub.SSO, and V.sub.DDO. An output driver of the device has an active p-channel pull up, and n-channel pulldown complementary pair configuration with their outputs tied to a common node, which is in turn tied to an I/O pad. A protection circuit for protecting the device from ESD events includes a series resistor disposed between the source of the n-channel pulldown transistor, and power supply bus V.sub.SSO. The protection circuitry includes a diode having its cathode connected to the I/O pad, and its anode connected to power supply bus V.sub.SSI. The pulldown transistor includes an n.sup.+ drain region, which is shared with the diode, wherein the diode and transistor are merged. The resistor between the pulldown transistor source, and power supply V.sub.SSO permits maintaining this merged structure. In an alternate embodiment, an n-well may be formed to underlie the p.sup.

Abstract: A method and apparatus for increasing the speed of a cascaded Content Addressable Memory (CAM) system by pre-charging the system match line of the CAM system are disclosed. The CAM system has (i) a plurality of CAM chips, (ii) a separate match output circuit for each CAM chip, (iii) a separate precharge circuit and pull-down circuit for each match output circuit and (iv) a system match line coupled to all of the match output circuits. Each of the precharge and pull-down circuits has an N-channel MOSFET. To increase the speed of the CAM system, the CAM system precharges the system match line so that the recovery time required for the system match line to change from a logic low to a logic high is minimized. Because each match output circuit has a precharge circuit, adding more CAM chips to the CAM system does not degrade the speed of the CAM system.

Abstract: A user configurable circuit contains clock logic, a switching element and a data path circuit. Input data is received in the switching element, and the switching element and the data path circuit constitute the entire data path for the circuit. A plurality of user configurable inputs are received to configure the circuit for a particular user application. The clock logic and the switching element implement a logic function that is configurable by the user configurable inputs. The logic function is pre-processed in the clock logic so that minimal delay occurs in the data path. In addition, the propagation delay through the switching element and the register is independent of the user configurable inputs. The user configurable circuit of the present invention has application for use as a macro cell for a programmable logic device permitting the user to configure the circuit as a D-type flip-flop, a T-type flip-flop. In addition, the user selects the polarity for the output circuit.

Abstract: An adaptive active filtering method and apparatus that detects changes in noise conditions and reduces the signal propagation speed as noise conditions worsen. This active filter has a level shifting inverter, which inverts the input signal and converts the logic levels of the input signal into chip logic levels. This inverted input signal is presented at the input of a driver inverter, which once again inverts the signal. This second inversion filters out input noise, because a voltage controlled device (which is attached to the driver inverter) reduces the switching speed of this inverter as the noise condition worsen; this reduction in switching speed reduces the propagation speed and thus filters out noise.

Abstract: A bi-directional control circuit for preventing the improper functioning of a pass transistor MN1 in a CMOS circuit due to abnormally high voltages on its source and drain nodes IO1 and IO2, involves controlling the voltage V1 on gate of MN1 using a gate node N1 that is coupled to supply voltage VCC under the control of two transistor pairs MN3, MN4 and MP3, MP4 that sense the voltages on IO1 and IO2, and an inverter pair MP2, MN2 having a voltage signal ENB input on its gates. If the voltages on nodes IO1 and IO2 both go high, MP3 and MP4 tend to turn OFF dropping gate voltage V1, via MP2, below VCC and tending to turn MN1 OFF. Leakage from node N1 in such event occurs through a small current bleed network formed by three transistors MN6, MN7, and MN8.

Abstract: The present invention concerns a method for making an identification mark on a silicon surface. In a preferred embodiment, the identification mark formed on the silicon surface does not substantially score the silicon. A silicon or silicon dioxide surface coated with an insulating layer is marked by laser scribing, leaving an exposed area on the silicon or the silicon dioxide. The exposed area on the silicon wafer is preferably not marked by the laser scribing. The exposed silicon surface is then oxidized by dry or wet oxidizing. The silicon oxide can be subsequently removed to leave an etched mark. The method reduces or eliminates the formation of stresses and silicon slag at the etched mark that can cause defects and reduce yield.

Abstract: A memory circuit with a low power programming voltage switch for reduced leakage current during a read operation. The apparatus includes a high voltage switch which, in a programming mode receives a high (e.g. programming) voltage and in another mode (reading) receives a normal range voltage, and a line driver which drivers a selection or non-selection voltage into word lines or column select lines into a memory array. During a read mode, the deselected line drivers and high voltage switches are operated in a reduced leakage current mode such that leakage current is forced through selected line drivers and their high voltage switches before being forced through the deselected line drivers such that the leakage current is limited to the number of selected line drivers.

Abstract: A CMOS circuit is disclosed for translating a signal from CML to CMOS logic voltage levels. The CMOS circuit includes two amplifier circuits coupled in parallel. The first amplifier circuit comprises of a programmable circuit and a CMOS inverter such that the CMOS inverter can be programmed "on" or "off" by the programmable circuit. The programmable circuit includes a programmable element which may be implemented using a fuse or floating gate technology. The second amplifying circuit comprises of a CMOS inverter. When the CMOS inverter in the first amplifier circuit is powered "on", the CMOS circuit is operating in a full power mode at high speed with both CMOS inverters operating. When the CMOS inverter in the first amplifier circuit is powered "off", the CMOS circuit is operating in a low power mode at a slower speed with only one CMOS inverter operating.