Abstract: A buffer utilizing the pseudo-ground hysteresis of the present invention contains first and second stage switching elements and a resistive element. The pseudo-ground hysteresis is implemented via a ground path from the switching elements. The first stage switching element is configured to have a first DC voltage trip point, and the second stage switching element is configured to have a second DC voltage trip point. As an input voltage, transitioning from a first state to a second state, is applied to the first stage switching element, a first current (I.sub.1), from the first stage switching element, and a second current (I.sub.2), from the second stage switching element, is generated. When the input voltage equals the first stage DC voltage trip point, the first and second stage switching elements transition. During the transition of the input voltage from the second state to the first state, the total current flowing through resistive element is reduced, and the voltage at the resistive element decreases.

Abstract: A testing circuit for reading and writing a greater number of data bits in parallel during a single clock cycle than through I/O data pins in a memory device. The testing circuit comprises at least one data-in buffer, a plurality of write buffers coupled to the data-in buffer, a plurality of write buses corresponding with the plurality of write buffers and coupled therewith, a plurality of read buses to retrieve data from a plurality of memory cells, a plurality of output buffers corresponding in number with the plurality of read buses and coupled therewith and at least one output driver. Additionally, the method of testing memory basically comprises the steps of inputting at least one data bit having the predetermined polarity into the memory device in order to produce a plurality of data bits having the predetermined polarity. These plurality of data bits are written in parallel into a plurality of memory cells.

Abstract: A memory is described that includes a main memory array having a plurality of main memory locations and a redundant memory array having a plurality of redundant memory locations. A main decoding circuit is coupled to the main memory array for decoding an address received from an external circuit to access a selected one of the plurality of main memory locations. A storage circuit is provided for pre-storing the address of the selected one of the plurality of main memory locations when the selected one of the plurality of main memory locations is defective. A redundant comparison circuit is coupled to the redundant memory array and the storage circuit for comparing the external address with the address stored in the storage circuit in order to access a selected one of the plurality of redundant memory locations.

Abstract: A process for filling vias formed in a dielectric layer is disclosed. First, a via is formed in a dielectric layer, exposing an underlying metallization layer having a seed layer thereon. A sputter etch is performed which removes a portion of the seed layer, including an oxidized surface layer. The material thus etched from the seed layer first seals the sidewall of via, preventing outgassing from occurring. The continued redeposition of the seed layer on the sidewall provides a nucleation site for selective deposition of a via fill material. Following the sputter etch, selective deposition of the via fill is performed. Since the deposition occurs from the sidewalls as well as on the bottom of the via, all vias become substantially filled at the same time.

Abstract: A phase-lock loop circuit including a voltage-controlled oscillator for generating a clock signal. The voltage-controlled oscillator includes a plurality of multiplexers coupled in series. The signal generated by the last multiplexer in the series is used as a clock signal. Each of the multiplexers in the series has a select input. Either a first signal or a second signal propagates through the series of multiplexers, depending on a select signal applied to the select inputs of the multiplexers. The second signal is the first signal with a predetermined delay. A 3-input multiplexer is connected to the first and last multiplexers in the series to the form a ring oscillator. The first or second signals output by the last multiplexer in the series is sent to an input of the 3-input multiplexer, and a test signal is sent to a third input of the 3-input multiplexer. The 3-input multiplexer also receives the select signal and a test mode signal.

Abstract: A sense amplifier circuit having a pair of complementary inputs and a pair of complementary outputs with voltage swing limiter and cross-coupled feedback to tail devices. The sense amplifier circuit comprises first differential amplifier for receiving the pair of complementary inputs to generate first output of the pair of complementary outputs. The first differential amplifier is coupled to a first current source device for biasing. The circuit also comprises second differential amplifier for receiving the pair of complementary inputs to generate second output of the pair of complementary outputs. The second differential amplifier is coupled to a second current source device for biasing. A voltage swing limiter is coupled to the pair of complementary outputs of the first and second differential amplifiers for limiting the voltage swing of the pair of complementary outputs. A feedback circuit is coupled to feed the outputs back to drive the other tail device.

Abstract: A programmable integrated circuit with adjustable speed/power characteristics having a primary current path which draws a predetermined amount of current; a plurality of impedance elements which generate a reference voltage which controls the current in the current path. One of a plurality of programmable switches is coupled in series, respectively, with one of the plurality of impedance elements, whereby each of the impedance elements can be connected or disconnected by setting its respective programmable switch, thereby adjusting the operating speed and the power consumption of the integrated circuit according to predetermined requirements. The programmable switches used in this invention preferably are erasable, programmable read-only memories.

Abstract: An asynchronous flag generator for generating an asynchronous flag having a minimum defined active pulse length. The asynchronous flag generator comprises an arbitrary length flag generator for generating an arbitrary length status flag signal from at least two asynchronous signals, one being a set flag signal and the other being a clear flag signal. A minimum pulse generator for generating a minimum pulse having a predefined pulse length upon initiation of the set flag signal. Combinational logic combines the arbitrary length status flag with the minimum pulse to generate an asynchronous status flag with a defined minimum active pulse length.

Abstract: An ECL circuit with power control is disclosed. The ECL circuit comprises a pair of emitter-coupled transistors with a current source transistor having its collector coupled to the coupled-emitters of the pair. Coupled in series with the base of the current source transistor is a first MOS transistor with its gate receiving an enable signal to control the first MOS transistor. As such, an activated first MOS transistor switches on the ECL circuit, and a de-activated first MOS transistor switches off the ECL circuit with no current through the current source transistor to provide a true power down of the ECL circuit. An ECL circuit for translating from CMOS to ECL levels is also disclosed. The ECL circuit comprises a pair of emitter-coupled transistors and first MOS transistor coupled in series with a first base of the pair at one end of the source/drain current path of the first MOS transistor.

Abstract: A multi-featured first-in-first-out (FIFO) memory device on a monolithic semiconductor integrated circuit chip. The FIFO device is bi-directional, in that the user may select the direction of data transfer through the device. The device may be configured in a transparent bypass mode of operation, wherein the FIFO memory array is bypassed, and data is transferred directed from either device input/output port to the other device input/output port. In another mode of operation allowing registered bypass operation, a byte of data may be written in an internal register from the device port being used to output data for later transfer to the device port presently being used to input data to the FIFO memory array. The FIFO device further includes a user-testable mode of operation, wherein data written into the FIFO memory array through a device input port may be read out of the same device input port.

Abstract: A transfer molding process for encapsulating a semiconductor device, such as an integrated circuit, in plastic. The semiconductor device is mounted on and electrically connected to a leadframe, the leadframe is placed in a preheated mold with the device and electrical connections disposed in a cavity and preheated thermosetting plastic molding compound is injected into the cavity through a gate located on the same side of the mold cavity as the device and electrical connections.

Abstract: An electrically programmable read only memory (EPROM) source bias circuit provides a bias voltage at the source of an EPROM transistor which may vary with EPROM processing characteristics. The source bias circuit includes a reference voltage generator which generates a reference voltage which varies with EPROM transistor cell conductivity, and a source bias element which sets the voltage on the source node of the EPROM transistor during programming. The circuit functions to provide a greater amount of source bias to a higher-conductivity EPROM cell during programming, and to apply a lower source bias voltage to low conductivity EPROM cells. Programming efficiency of the EPROM transistor is improved, and yield of EPROM devices employing the circuit is enhanced.

Abstract: A resettable SRAM architecture and method that eliminates the need to reset all memory cells in the data memory array and requires only the resetting of one flag bit per block of data. This prevents superfluous activation of access circuits and memory cell transistors, thereby reducing power consumption and parasitic noise.

Abstract: The present invention minimizes the noise voltage associated with the switching of output driver transistors of integrated cicruits caused by the rapid change in value of the current, expressed by the term di/dt, from the load into the driver transistors through the package leads. The present invention uses a programmable coarse current control (CCC) circuit and a programmable fine current control (FCC) circuit that control the pull-down output transistors. The FCC creates two time periods, after which it prevents the CCC from controlling an output pull-down transistor. The FCC and the CCC are used to reduce the di/dt dependent voltage noise by controlling the slope and the shape of the output voltage pull-down characteristics.

Abstract: An improved MOS memory circuit using an MOS clamp circuit on the bitlines which turns on when the voltage on a bitline exceeds a predetermined voltage, thereby drawing current from the bitline to remove excess charge and return the bitline to the predetermined voltage. The clamp circuit of this invention allows prompt read access because reading is not substantially delayed by the excess bitline charge.

Abstract: An integrated circuit device having a memory array of memory cells in which the total number N of unique available memory addresses is a power of two, yet wherein neither the number of columns nor the number of rows of cells is a power of two. This permits the chip die size and height/width ratio to be optimized. The device further includes a circuitry for generating address selection signals, providing a total number of unique addresses equal to N, leaving unused some of the memory cells comprising the array.

Abstract: The present invention is a method of creating a ring surrounding a chip carrier having a lead frame premolded to a carrier body or housing. The ring is comprised of a first premolded section having a first predetermined shape and a second premolded section having a second predetermined shape. A non-conductive adhesive material is applied to a mating side of each of said sections. These first and second sections are combined to form the ring in which certain portions of the first section mate into the second section through matching holes in the metal lead frame of the chip carrier package. The resulting chip carrier ring is positioned in a short distance from the carrier body relative to the length of any of the four sides of the carrier body in order to gain mechanical strength provided by the plurality of leads, thus avoiding the substantial bending of individual leads.

Abstract: The present invention relates to an MOS integrated circuit employing a plurality of floating gate type, erasable, programmable read-only memory (EPROM) devices. The improvement of the invention comprises a clamp coupled to the control gates of the EPROMs, the clamp being adapted to clamp the voltage on these gates in the range of the typical supply voltage for the circuit, whereby, after an EPROM cell is properly charged, it will continue to read out as a properly charged cell even though some of the actual charge on its floating gate may have leaked.

Abstract: An improved architecture for and a method of operating a high speed synchronous state machine is disclosed having a programmable logic array receiving inputs from dedicated input registers and having an input/output macrocell which includes two state registers and two input registers, and two transparent latches and two feedback multiplexers. The outputs from the input registers are multiplexed through an input multiplexer and the input registers may be clocked at different input clock rates than the state clock which clocks the state registers.

Abstract: The transient voltage spike generated by the distributed inductance of the packaging wires on an IC chip is reduced by slowing the on-to-off switching speed of the output transistors. The longer switching time provides a longer dt in the di/dt current through the wires during turn off. A two stage slew control circuit controls the initial stage and final stage of the slew period with an initial fast stage to advance the start of output transistor turn off and a slow stage for extending the turn off slew period during the final stage of the slew period.