Abstract: Systems, methods, and devices reduce interference experienced by wireless communications devices. Methods include receiving a first signal from a first transceiver, the first signal being compatible with a first communications protocol, and configuring a filter based, at least in part, on the received first signal, the filter being communicatively coupled to a second transceiver collocated in a same wireless communications device as the first transceiver. The methods further include receiving a second signal, the second signal being compatible with a second communications protocol, and filtering the second signal to remove at least some components of the first signal from the second signal, the filtering reducing at least some interference from the first signal with the second signal. The methods also include providing the filtered second signal to the second transceiver.

Abstract: An IC controller for USB Type-C device includes an error amplifier (EA), which includes an EA output coupled to a PWM comparator of a buck-boost converter; a first transconductance amplifier to adjust a current at the EA output, the first transconductance amplifier operating in a constant voltage mode; and a second transconductance amplifier to adjust the current at the EA output, the second transconductance amplifier operating in a constant current mode. A first set of programmable registers is to store a first set of increasingly higher transconductance values. A second set of programmable registers is to store a second set of increasingly higher transconductance values. Control logic is to: cause the first transconductance amplifier to operate while sequentially using transconductance values stored in the first set of programmable registers; and cause the second transconductance amplifier to operate while sequentially using transconductance values stored in the second set of programmable registers.

Abstract: An error amplifier includes an output pin coupled to a pulse width modulation (PWM) comparator of a buck-boost converter. A first transconductance amplifier adjusts an output current at the output pin and operates in a constant voltage mode. The first transconductance amplifier includes a first positive input to receive a first voltage reference and a first negative input coupled to a tap point of a voltage divider coupled between a voltage bus and a ground of the buck-boost converter. A second transconductance amplifier also adjusts the output current at the output pin and operates in a constant current mode. The second transconductance amplifier includes a second positive input to receive a second voltage reference and a second negative input coupled to a current sense amplifier, the current sense amplifier being coupled to a sense resistor positioned inline along the voltage bus.

Abstract: A controller includes a buck gate driver coupled to first high-side switch and first low-side switch of a buck-boost (BB) converter. A zero crossing detection (ZCD) comparator is coupled to first low-side switch. The ZCD comparator is to, while the BB converter operates in buck mode: detect zero current flow through inductor; and turn off first low-side switch in response to detecting the zero current. A boost gate driver is coupled to second high-side switch and second low-side switch of the BB converter. A reverse current detection (RCD) comparator coupled to second high-side switch. The RCD comparator is to, while the BB converter operates in boost mode: detect zero current flow through second high-side switch; and turn off second high-side switch in response to detecting the zero current.

Abstract: A mode-transition architecture for USB Type-C controllers is described herein. In an example embodiment, an integrated circuit (IC) controller includes controller includes a controller coupled to a slope compensation circuit, the controller to cause the slope compensation circuit to apply a first slope compensation to the input current in a first mode in which the buck-boost converter is operating in a discontinuous conduction mode (DCM). The controller detects a transition of the buck-boost converter from a first mode having a first duty cycle to a second mode and causes the slope compensation circuit to apply a second slope compensation to the input current. The second slope compensation starts at a maximum offset of the first slope compensation.

Abstract: An apparatus includes a first high-side driver of a buck-boost converter, the first high-side driver powered between a first bootstrap voltage (VBST1) and a first output voltage of a first high-side switch driven by the first high-side driver. A second high-side driver is powered between a second bootstrap voltage (VBST2) and a second output voltage of a second high-side switch driven by the second high-side driver. A comparator is to detect VBST1 drop below a threshold value with respect to the first output voltage when the buck-boost converter is in boost mode. A leakage control circuit is to boost, using VBST2 as a voltage source, VBST1 each cycle of boost mode in which an output of the comparator is enabled.

Abstract: Disclosed are solutions for communicating with USB-C/PD systems over standard communication interfaces in automotive, aviation, industrial, or other applications. In one aspect, the solutions facilitate a controller of the automotive Local Interconnect Network (LIN) bus such as a vehicle electronic control unit (ECU) to configure, control, and monitor charging and fault data of ports of a USB-C/PD system over the existing vehicle network. The USB-C/PD system may decode a message frame to determine a frame type. If the message frame is a request frame, control data is received from the ECU over the LIN bus to control the operations of the USB-C/PD port. If the message frame is a response frame, the USB-C/PD port transmits response data that monitors the operations of the USB-C/PD port to the ECU over the LIN bus. Advantageously, the USB-C/PD system may be easily integrated into existing communication networks, providing a cost-effective and scalable solution.

Abstract: A multi-port USB Power Delivery Type-C (USB-C/PD) power converter for switching clock phase shifts is described herein. The multi-port USB-C/PD power converter includes a first PD port, a second PD port, and a power controller coupled to the first and second PD ports. The power controller includes a first phased clock generator to generate a first phase-shifted clock signal by shifting a clock signal by a first phase with respect to a reference clock signal, and a second phased clock generator to generate a second phase-shifted clock signal to generate a second phased-shifted clock signal by shifting the clock signal by a second phase with respect to the reference clock signal. The first PD port and the second PD port output power in response to a first control signal based on the first phase-shifted clock signal and a second control signal based on the second phase-shifted clock signal, respectively.

Abstract: An IC controller for a USB Type-C device includes a register that is programmable to store a pulse width and a frequency. A buck-boost converter of the controller includes a first high-side switch and a second high-side switch. Control logic is coupled to the register and gates of the first/second high-side switches. To perform a soft start in one of buck mode or boost mode, the control logic: causes the second high-side switch to operate in diode mode; retrieves values of the pulse width and the frequency from the register; causes the first high-side switch to turn on using pulses having the pulse width and at the frequency; detects an output voltage at the output terminal of the buck-boost converter that exceeds a threshold value; and in response to the detection, transfers control of the buck-boost converter to an error amplifier loop coupled to the control logic.

Abstract: A mode-transition architecture for USB controllers is described herein. In an example embodiment, an integrated circuit (IC) controller includes a controller coupled to a slope compensation circuit, the controller to detect a transition of a buck-boost converter from a first mode having a first duty cycle to a second mode having a second duty cycle that is less or more than the first duty cycle. The controller controls the slope compensation circuit to nullify an error in an output caused by the transition. The controller can cause the slope compensation circuit to apply a charge stored in a capacitor during a first cycle to start a second cycle with a higher voltage than the first cycle.

Abstract: A multi-port Universal Serial Bus Type-C (USB-C) controller with ground and supply cable compensation technologies is described. A USB-C controller includes a first power control circuit (PCU) coupled to a system ground terminal and a first ground terminal and a second PCU coupled to the system ground terminal and a second ground terminal. The first PCU receives a first ground signal indicative of a first ground potential at a first USB-C connector and adjusts a first power voltage line (VBUS) signal on the first VBUS terminal based on the first ground signal and the system ground. The second PCU receives a second ground signal indicative of a second ground potential at a second USB-C connector and adjusts a second VBUS signal on the second VBUS terminal based on the second ground signal and the system ground.

Abstract: Systems and methods provide a first sample of audio data and detect speech onset in the first sample of the audio data. Responsive to detecting the speech onset, systems and methods switch from capturing second samples of the audio data at first intervals, to capturing the second samples of the audio data at second intervals. Systems and methods provide contiguous audio data using the second samples of the audio data captured at the first intervals and at least one captured portion of the second samples of the audio data captured at the second intervals.

Abstract: In an example embodiment, a Universal Serial Bus (USB) Type-C cable comprises a USB Type-C connector and an IC controller coupled thereto. The IC controller comprises a terminal coupled to a VCONN line of the USB Type-C cable, a transistor coupled between the terminal and an internal power supply of the IC controller, a resistive element coupled between the terminal and a control terminal of the transistor, and control logic. The IC controller is to: power on the transistor from a voltage, received at the terminal, falling across the resistive element; power on the internal power supply in response to the voltage being passed through the transistor; power up the IC controller in response to powering on the internal power supply; and operate the control logic to fully power on the transistor, and thus enter an active mode of the IC controller.

Abstract: Implementations disclosed describe techniques to effectuate operating mode changes of a wireless connection between a first communication device (CD) and a second CD. In an example embodiment, the disclosed techniques may include detecting, by a wireless network controller of the second CD, an indication that the first CD has requested the operating mode change from a first operating mode to a second operating mode. The disclosed techniques may further include modifying a transmission information (TI) associated with one or more frames in a transmission queue of the second CD, the TI comprising a representation used by a physical layer of the second CD to configure transmission of a respective frame to the first CD, wherein the one or more frames in the transmission queue have been previously programmed with a first-mode TI, and wherein modification of the TI is to a second-mode TI.

Abstract: In an example embodiment, a device comprises a non-volatile memory and wear leveling control circuitry. The non-volatile memory comprises logical memory sectors mapped to physical memory sectors, and a supervisory memory sector configured to store a mapping of the logical memory sectors to memory partitions with user-defined boundaries. The wear leveling control circuitry is configured to: receive and store, in the mapping, wear leveling parameters based on user input, where each memory partition is associated with a wear leveling parameter indicating whether that memory partition is excluded from wear leveling; and determine and apply, to the non-volatile memory, wear leveling characteristics based on the wear leveling parameters, where the wear leveling characteristics identify an amount of wear leveling allowed for each of the memory partitions.

Abstract: An apparatus includes a non-volatile memory (NVM) device coupled to a host, the NVM device including a processing device to: receive a communication packet from a server via the host computing system that is coupled to the NVM device and communicatively coupled to the server, the communication packet comprising clear text data that requests to initiate secure communications; perform a secure handshake with the server, via communication through the host computing system, using a secure protocol that generates a session key; receive data, via the host computing system, from the server within a secure protocol packet, wherein the data is inaccessible to the host computing system; authenticate the data using secure protocol metadata of the secure protocol packet; optionally decrypt, using the session key, the data to generate plaintext data; and store the plaintext data in NVM storage elements of the NVM device.

Abstract: A semiconductor device having a substrate, a dielectric layer, a polycrystalline silicon (“poly”) resistor, a drain, and a source is disclosed. After implantation, the poly resistor may have a lateral doping profile with two peaks, one near each edge of the poly resistor, and a trough near the middle of the poly resistor. Such a doping profile can allow the poly resistor to have a resistance that is insensitive to small variations in critical dimension of the poly resistor. The resistance of the poly resistor may be determined by the doping dose of the tilted implant used to form the poly resistor. The tilted implant may be used to form the drain and the source of a transistor substantially simultaneously as forming the poly resistor.

Abstract: One embodiment includes and I/O bus including a signal line coupled to a signal source and multiple line switches, each line switch to couple a corresponding I/O port to the signal line. Switch logic coupled to the I/O bus may programmatically switch the multiple line switches to couple at least one of the signal source and measurement circuitry to the respective I/O port.

Abstract: Techniques by a wireless to estimate the position of a remote device are disclosed. A main receiver of the wireless device may determine multiple first phase values of the RF signal received through a first antenna during multiple time intervals. An auxiliary receiver may determine multiple second phase values of the RF signal received through an array of auxiliary antennas during the multiple time intervals. Each of the second phase value may correspond to the RF signal received through one antenna of the array during one of the time interval. The wireless device may determine an oscillator offset between a local oscillator of the main transceiver and a local oscillator of the auxiliary receiver. The wireless device may estimate an angle of arrival (AoA) of the RF signal or a distance based on the multiple first phase values and the multiple second values by compensating for the oscillator phase offset.

Abstract: A method can include modulating an amplified analog signal into a digital data stream, filtering the digital data stream with a first filter, generating gain control values associated with amplified analog signal based on the filtered data stream with the first filter and filtering the digital data stream with a second filter, and generating output digital values associated with the amplified analog signal based on the filtered data stream with the second filter. Corresponding systems and devices are also disclosed.