Patents Assigned to Cypress Semiconductor
  • Memory device resilient to cyber-attacks and malfunction
    Patent number: 11249689
    Abstract: A non-volatile memory (NVM) integrated circuit device includes an NVM array of memory cells partitioned into a first physical region to store a first firmware stack and a second physical region to store a second firmware stack. The NVM integrated circuit device also includes a processing device that enables a host microcontroller to execute in place the first firmware stack stored within a first set of logical addresses that is mapped to the first physical region. The processing device tracks accesses, by the host microcontroller, to the first set of logical addresses. The processing device, in response to detecting one of a certain number or a certain type of the accesses by the host microcontroller, initiates a recovery operation including to remap the first set of logical addresses to the second physical region.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: February 15, 2022
    Assignee: Cypress Semiconductor Corporation
    Inventors: Sergey Ostrikov, Stephan Rosner, Avi Avanindra, Hans Van Antwerpen
  • DEVICES, SYSTEMS AND METHODS FOR ACCESSING RANDOM ACCESS RESOURCE UNITS OF A WIRELESS CHANNEL
    Publication number: 20220039162
    Abstract: A method can include wireless device operations, including receiving a trigger communication that identifies available random access resource units (RA RUs), the RA RUs being portions of transmission channel for a wireless system. In response to a back-off value and a number of available RA RUs, selecting or not selecting one RA RU as a transmission RA RU. In response to not selecting a transmission RA RU, monitoring for wireless responses following the trigger communication to determine unselected RA RUs, designating one unselected RA RUs as an alternate RA RU; and transmitting uplink data on the alternate RA RU. The unselected RA RUs comprise any RA RUs that remain after other wireless devices have selected RA RUs in response to the trigger communication. Corresponding devices and systems are also disclosed.
    Type: Application
    Filed: July 26, 2021
    Publication date: February 3, 2022
    Applicant: Cypress Semiconductor Corporation
    Inventors: Saishankar Nandagopalan, Kiran Uln
  • Apparatus, systems, and methods for battery life based wireless communication scheduling
    Patent number: 11240755
    Abstract: Systems and methods compare a first battery life value associated with a first wireless device with a second battery life value associated with a second wireless device. Based on the comparison, systems and methods adjust a communication schedule by allocating timeslots of the communication schedule to the first wireless device and transmit the adjusted communication schedule to the first wireless device.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: February 1, 2022
    Assignee: Cypress Semiconductor Corporation
    Inventors: Xianmin Wang, Hui Luo, Hongwei Kong
  • DEVICES, SYSTEMS AND METHODS FOR LOW LATENCY DATA TRANSMISSION IN WIRELESS NETWORK
    Publication number: 20220022203
    Abstract: Embodiments can include a method in which a transmission duration for data frames to a plurality of different receiving devices is determined by a transmitting device. The transmission duration can include at least interframe spacings that separate the data frames from one another. The transmitting device can transmit a control message over a medium to reserve the medium for the transmission duration. The data frames can then be sequentially transmitted by the transmitting device to the plurality of receiving devices during the transmission duration. The transmitting device can operate according to a contention based protocol. Related devices and systems are also disclosed.
    Type: Application
    Filed: September 20, 2021
    Publication date: January 20, 2022
    Applicant: Cypress Semiconductor Corporation
    Inventors: Rajendra Kumar Gundu Rao, Kamesh Medapalli
  • Low-emissions touch controller
    Patent number: 11226706
    Abstract: Technology directed to low-emissions touch controller in in-cell touch display systems is described. One in-cell touch controller includes a signal generator circuit that is configured to generate a sense signal according to a sensing function, the sense signal including a windowed sinusoidal waveform. The controller generates a transition signal to transition the in-cell touch display between a display function and the sensing function. The controller drives the sense signal and the transition signal on common voltage (VCOM) layer of electrodes during a touch scanning interval. During a display function interval an integrated display driver is configured to drive a first signal on the VCOM layer of electrodes during a display function interval.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: January 18, 2022
    Assignee: Cypress Semiconductor Corporation
    Inventors: Viktor Kremin, Oleksandr Pirogov, Jens Weber, Yarsolav Lek, Daniel O'Keeffe, Brendan Lawton, Khosrov D Sadeghipour, Gaurav Panchanan, Andrew Kinane
  • Power-efficient sync-rectifier gate driver architecture
    Patent number: 11223270
    Abstract: A synchronous switching scheme with adaptive slew control in order to adiabatically charge and discharge a capacitor to recycle charge and generate a boosted voltage on the gate of the synchronous rectifier field effect transistor (FET) is described. In one embodiment, an apparatus includes a synchronous rectifier FET coupled to a transformer, and a secondary-side controller coupled to the synchronous rectifier FET. The secondary-side controller includes a synchronous rectifier gate driver (SRGD) coupled to a gate of the synchronous rectifier FET. The SRGD is to drive the synchronous rectifier FET using the capacitor and an adaptive slew rate, and to adiabatically charge and discharge the capacitor.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: January 11, 2022
    Assignee: Cypress Semiconductor Corporation
    Inventors: Karri Rajesh, Arun Khamesra
  • METHOD FOR IOT DEVICE TO STAGGER TX AND SAVE POWER
    Publication number: 20220007220
    Abstract: Disclosed are methods and systems for delaying packet transmissions over a wireless communication channel until a more favorable channel condition is detected. A device may measure a channel metric when it receives periodic beacon signals. The device may compare the channel metric against a programmed metric threshold. If the channel metric is less than the metric threshold, the device may delay the transmission of a packet until a later transmission window or transmit opportunity (TXOP) when the channel metric rises above the metric threshold, indicating the presence of a more favorable condition for transmission, or until a preconfigured timeout period elapses before the more favorable condition is found.
    Type: Application
    Filed: July 16, 2021
    Publication date: January 6, 2022
    Applicant: Cypress Semiconductor Corporation
    Inventors: Prasanna Kumar Sethuraman, Rajendra Kumar Gundu Rao, Ayush Sood, Paul Strauch
  • PROVIDING A BASELINE CAPACITANCE FOR A CAPACITANCE SENSING CHANNEL
    Publication number: 20210405848
    Abstract: A capacitance-sensing circuit may include a channel input associated with measuring a capacitance of a unit cell of a capacitive sense array. The capacitance-sensing circuit may also include a capacitive hardware baseliner that is coupled to the channel input. The capacitive hardware baseliner generates a baseline current based on a time constant of the channel input associated with the measuring of the capacitance of the element of the capacitive sense array using the programmable baseline resistor. The capacitive hardware baseliner provides the baseline current at the channel input to provide a charge for a sense capacitor. A change in the charge of the sense capacitor is provided by the baseline current indicating a presence of a tough object proximate to the element.
    Type: Application
    Filed: June 30, 2021
    Publication date: December 30, 2021
    Applicant: Cypress Semiconductor Corporation
    Inventors: Denis Ellis, Kaveh Hosseini, Timothy Williams, Gabriel Rowe, Roman Ogirko, Brendan Lawton
  • WLAN DECODABILITY-BASED FRAME PROCESSING FOR POWER SAVING
    Publication number: 20210410225
    Abstract: Methods, apparatus and systems are disclosed for receiving an IEEE 802.11 frame at a WLAN station, determining whether the frame is decodable and addressed to the WLAN station, and entering a reduced power state if the frame is not decodable or not addressed to the WLAN station.
    Type: Application
    Filed: June 26, 2020
    Publication date: December 30, 2021
    Applicant: Cypress Semiconductor Corporation
    Inventors: Ayush Sood, Suprojit Mukherjee, Prasanna Kumar Sethuraman, Sri Ramya Thota, Kalaivani K
  • NOVEL PROGRAMMABLE CHOPPING ARCHITECTURE TO REDUCE OFFSET IN AN ANALOG FRONT END
    Publication number: 20210408986
    Abstract: An integrated circuit can include an amplifier coupled to receive an analog input signal, an anti-aliasing filter (AAF) coupled to an output of the amplifier, a buffer circuit coupled to an output of the AAF, a sigma-delta modulator configured to generate a digital data stream in response to an output of the buffer, and a plurality of chopping circuits nested within one another, including a first pair of chopping circuits having at least the amplifier disposed therebetween and configured to remove offset in the analog input signal, and a second pair of chopping circuit having at least the first pair of chopping circuits disposed therebetween. The amplifier, AAF, sigma-delta modulator, and chopping circuits can be formed with the same integrated circuit substrate. Corresponding methods and systems are also disclosed.
    Type: Application
    Filed: June 26, 2020
    Publication date: December 30, 2021
    Applicant: Cypress Semiconductor Corporation
    Inventors: Erhan Hancioglu, Eashwar Thiagarajan, Eric Mann, Harold Kutz, Vaibhav Ramamoorthy, Rajiv Singh, Amsby Richardson, JR.
  • LOCAL INTERCONNECT NETWORK (LIN) DRIVER CIRCUIT
    Publication number: 20210409017
    Abstract: A driver circuit and corresponding methods and systems are disclosed, the driver circuit comprises a signal generation circuit to generate a linearly varying signal at a first node based on a clock signal and an output transistor to receive the linearly varying signal and output a drive signal to a bus. A buffer amplifier is coupled between the first node and a gate of the output transistor to disable the gate capacitance of the output transistor. The driver circuit further comprises a capacitor coupled between the first node and a feedback node of the driver circuit such that the Miller effect occurs at the capacitor and a slew rate for the drive signal is generated at the feedback node.
    Type: Application
    Filed: March 1, 2021
    Publication date: December 30, 2021
    Applicant: Cypress Semiconductor Corporation
    Inventor: Toru Miyamae
  • METHOD FOR FAST DETECTION AND AUTOMATIC GAIN ADJUSTMENT IN ADC BASED SIGNAL
    Publication number: 20210409034
    Abstract: A method can include modulating an amplified analog signal into a digital data stream, filtering the digital data stream with a first filter, generating gain control values associated with amplified analog signal based on the filtered data stream with the first filter and filtering the digital data stream with a second filter, and generating output digital values associated with the amplified analog signal based on the filtered data stream with the second filter. Corresponding systems and devices are also disclosed.
    Type: Application
    Filed: October 16, 2020
    Publication date: December 30, 2021
    Applicant: Cypress Semiconductor Corporation
    Inventors: Eashwar Thiagarajan, Erhan Hancioglu, Eric N. Mann, Harold Kutz, Amsby D. Richardson, JR., Rajiv Singh
  • Programmable shunt regulator
    Patent number: 11209847
    Abstract: Example apparatus, systems, and methods receive, by a current digital-to-analog converter (DAC) of a shunt regulator, a first digital code indicative of a first programmable power supply command specifying a first programmable output voltage (Vbus) to be delivered to a voltage bus of a USB-compatible device. The programmable power supply command is compatible with a universal serial bus—power delivery (USB-PD) standard. Responsive to receipt of the first digital code, adjust, by the current DAC, a sink current delivered to a feedback node to adjust an output voltage to the first Vbus for dynamic programmability. The feedback node is coupled to a first input of an amplifier of the shunt regulator and the first Vbus is programmable.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: December 28, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventor: Pavan Kumar Kuchipudi
  • Securing data logs in memory devices
    Patent number: 11210238
    Abstract: An apparatus including non-volatile memory to store a forensic key and data, the data received from a host computing system. A processing device is coupled to the non-volatile memory and is to: allow writing the data, by the host computing system, to a region of the non-volatile memory; in response to a lock signal received from the host computing system, assert a lock on the region of the non-volatile memory, the lock to cause a restriction on access to the region of the non-volatile memory by an external device; and provide unrestricted access, by the external device, to the region of the non-volatile memory in response to verification of the forensic key received from the external device.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: December 28, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Avi Avanindra, Stephan Rosner, Cliff Zitlaw
  • SYSTEMS AND METHODS FOR DOWNLOADING CODE AND DATA INTO A SECURE NON-VOLATILE MEMORY
    Publication number: 20210399899
    Abstract: An example secure embedded device includes a secure non-volatile memory coupled to a processor. The processor provides a scramble or cipher key and uses a scramble algorithm or a cipher algorithm to scramble or cipher information received from an external device into transformed information. The processor writes a least a portion of the transformed information to a plurality of memory locations of the secure non-volatile memory. The plurality of memory locations is based on the scramble or cipher key.
    Type: Application
    Filed: July 8, 2021
    Publication date: December 23, 2021
    Applicant: Cypress Semiconductor Corporation
    Inventors: Arnaud Boscher, Nicolas Prawitz
  • PSEUDO-DIGITAL LIGHT EMITTING DIODE (LED) DIMMING WITH SECONDARY-SIDE CONTROLLER
    Publication number: 20210400789
    Abstract: Pseudo-digital light-emitting diode (LED) with secondary-side flyback control is described. In one embodiment, a Digital Addressable Lighting Interface (DALI) compatible driver includes a secondary-side controller coupled to a secondary winding of a transformer and coupled to a light-emitting element. The secondary-side controller includes a DALI-compatible interface to receive information. The secondary-side controller communicates a control signal with a primary-side controller via a galvanically-isolated link. The primary-side controller is coupled to a primary winding of the transformer. The DALI-compatible driver modifies a light output of the light-emitting element in response to the information.
    Type: Application
    Filed: June 23, 2020
    Publication date: December 23, 2021
    Applicant: Cypress Semiconductor Corporation
    Inventors: Hariprasad Palliyil Chundethodiyil, Prasanna Venkateswaran Vijayakumar, Aniket Shashikant Mathad
  • Pseudo-digital light emitting diode (LED) dimming with secondary-side controller
    Patent number: 11206727
    Abstract: Pseudo-digital light-emitting diode (LED) with secondary-side flyback control is described. In one embodiment, a Digital Addressable Lighting Interface (DALI) compatible driver includes a secondary-side controller coupled to a secondary winding of a transformer and coupled to a light-emitting element. The secondary-side controller includes a DALI-compatible interface to receive information. The secondary-side controller communicates a control signal with a primary-side controller via a galvanically-isolated link. The primary-side controller is coupled to a primary winding of the transformer. The DALI-compatible driver modifies a light output of the light-emitting element in response to the information.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: December 21, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Hariprasad Palliyil Chundethodiyil, Prasanna Venkateswaran Vijayakumar, Aniket Shashikant Mathad
  • Accurate peak detection architecture for secondary controlled AC-DC converter
    Patent number: 11201556
    Abstract: An AC-DC converter with synchronous rectifier (SR) architecture and method for operating the same are described. Generally, a secondary side integrated circuit (IC controller of the AC-DC converter includes a peak-detector block coupled to detect peak voltages sensed on a SR-SNS pin. The peak-detector block comprises a peak comparator, a sample-and-hold (S/H) circuit, and a DC offset circuit. The peak comparator is coupled to receive a sinusoidal input from the SR-SNS pin. The S/H circuit is coupled to sample the sinusoidal input and to provide a peak sampled voltage. The DC offset voltage circuit is coupled between the output of the S/H circuit and a reference voltage input of the peak comparator to subtract a DC offset voltage from the peak sampled voltage.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: December 14, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Saravanan Murugesan, Karri Rajesh, Pulkit Shah, Arun Khamesra, Hariom Rai
  • Local interconnect network (LIN) driver circuit
    Patent number: 11201617
    Abstract: A driver circuit and corresponding methods and systems are disclosed, the driver circuit comprises a signal generation circuit to generate a linearly varying signal at a first node based on a clock signal and an output transistor to receive the linearly varying signal and output a drive signal to a bus. A buffer amplifier is coupled between the first node and a gate of the output transistor to disable the gate capacitance of the output transistor. The driver circuit further comprises a capacitor coupled between the first node and a feedback node of the driver circuit such that the Miller effect occurs at the capacitor and a slew rate for the drive signal is generated at the feedback node.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: December 14, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventor: Toru Miyamae
  • Agile Interference Detection and Mitigation for Multicarrier Phase Ranging Systems
    Publication number: 20210373149
    Abstract: A multicarrier phase ranging system and method are provided. Generally, the method includes performing a handshake between first and a second transceiver to negotiate a list of channels and a start-time for a multicarrier phase ranging process. The process includes in a first cycle exchanging a Constant Tone (CT) between the first and second transceiver in a first epoch on a first channel, and processing the CT received in the first and second transceiver to measure a difference in phase between the CT received and a reference signal. The CT received is checked for interference using software or hardware in either or both of the first and second transceiver. If no interference is detected the first and second transceiver switch to another channel and exchange the CT at a next epoch. If interference is detected, at least one channel is skipped for at least a subsequent epoch.
    Type: Application
    Filed: September 24, 2020
    Publication date: December 2, 2021
    Applicant: Cypress Semiconductor Corporation
    Inventors: Pouria Zand, Kiran Uln