Abstract: A method and processor program product for performing an upgrade of a program on a processor are provided. An upgraded version of the program is received into the processor and a backup of the program is created in memory associated with the processor. The upgraded version of the program is then installed and the processor is rebooted. Prior to initializing other application drivers, a reboot driver checks if the state of the processor is correct. If the reboot driver determines that the state of the processor is incorrect, the system reverts to the backup of the program. In alternative embodiments, if the reboot driver determines that the state is incorrect, the system inhibits the loading of other application drivers. Additionally, the reboot driver may set a counter to indicate the number of times that the processor is rebooted. If the counter has not reached a predetermined threshold, the system attempts to reboot the processor with the upgraded version of the program.

Abstract: A high availability computer system and methodology including a backplane, having at least one backplane communication bus and a diagnostic bus, a plurality of motherboards, each interfacing to the diagnostic bus. Each motherboard also includes a memory system including main memory distributed among the plurality of motherboards and a memory controller module for accessing said main memory interfacing to said motherboard communication bus. Each motherboard also includes at least one daughterboard, detachably connected to thereto. The motherboard further includes a backplane diagnostic bus interface mechanism interfacing each of the motherboards to the backplane diagnostic bus; a microcontroller for processing information and providing outputs and a test bus controller mechanism including registers therein.

Abstract: A MOSFET, an op-amp, a comparator circuit, and voltage dividers with capacitors are employed in combination to effectuate a soft-start switch with current limiting. The transconductance of the MOSFET is employed so that no sense resistor is required. The MOSFET and op-amp are configured as a closed-loop feedback circuit in which the output of the op-amp is coupled to the gate of the MOSFET and the inverting input of the op-amp is coupled to the output of the soft-start switch via a voltage divider. A first RC circuit provides a voltage to the non-inverting input of the op-amp which can be triggered to gradually rise from a value close to zero to some reference voltage so as to soft-start a load. Current limiting means are effectuated by a comparator circuit and voltage dividers with capacitors.

Abstract: A very fast, memory efficient, highly expandable, highly efficient CCNUMA processing system based on a hardware architecture that minimizes system bus contention, maximizes processing forward progress by maintaining strong ordering and avoiding retries, and implements a full-map directory structure cache coherency protocol. A Cache Coherent Non-Uniform Memory Access (CCNUMA) architecture is implemented in a system comprising a plurality of integrated modules each consisting of a motherboard and two daughterboards. The daughterboards, which plug into the motherboard, each contain two Job Processors (JPs), cache memory, and input/output (I/O) capabilities. Located directly on the motherboard are additional integrated I/O capabilities in the form of two Small Computer System Interfaces (SCSI) and one Local Area Network (LAN) interface. The motherboard includes main memory, a memory controller (MC) and directory DRAMs for cache coherency.

Abstract: A heatsink assembly for removing at least some of the heat produced by an electronic component during use includes a heatsink, a heatpipe mounted on the heatsink and a plurality of thin, elongated fins mounted on the heatpipe. The heatsink is an elongated, generally rectangularly-shaped body and comprises a bottom surface, a top surface and a central, cylindrical channel formed in the top surface. A pair of clip recesses are formed in the top surface of the heatsink on opposite sides of the central channel. A first set of thin, elongated fins and a second set of thin, elongated fins are also formed in the top surface of the heatsink and serve to remove at least some of the heat transferred onto the heatsink. The heatpipe comprises an evaporator section and a condenser section. The evaporator section of the heatpipe is disposed tightly within the central channel of the heatsink so as to maximize the transfer of heat from the heatsink to the heatpipe.

Abstract: An electronic device supplied power from either a single rechargeable battery or four non-rechargeable batteries. The single rechargeable battery is preferably a 4.8 volt, DURACELL DR-121 rechargeable battery which includes a first end having positive and negative terminal contacts, a pair of recharging contacts and a key. Each of the four non-rechargeable batteries are preferably AA size, lithium batteries and are configured so that a first pair of batteries in series are in parallel with a second pair of batteries in series. The electronic device comprises a housing shaped to include a battery cavity which can accept either type of battery source. The battery cavity comprises a bottom wall, a front end wall, a back end wall and a pair of sidewalls. One of the sidewalls includes a slot which is sized and shaped to accept the key of the rechargeable battery, the slot enabling the rechargeable battery to be inserted in the battery cavity only in its proper orientation relative to the battery cavity.

Abstract: A method for use in a multiprocessor computer system where data objects larger than the address space of a single task are mapped in main memory and the translation lookaside buffer (TLB) is maintained by user mode software is disclosed. The method uses lazy TLB updating that allows stale data to stay in the TLB until it needs to be purged.

Abstract: A system and method for controlling the access of users to a trusted computer system using an authentication and authorization database, containing information used to authenticate human users and information establishing what each user can do, and a number of software processes, including session initiation, authorization, credentials and database management daemons. The software processes are implemented in an independent fashion to prevent any process from performing an operation that would affect another process in an unauthorized way.

Abstract: A recovery method and fail-over switch for use in a data storage system in which a plurality of data storage devices are connected to each of two communication paths. The switch may route requests to either of the two communication paths. Switching may be accomplished by two fail-over switches connected to each other and each in connection with one of the two communication paths. With one data storage controller in communication with the data storage devices over a first path and a second data storage controller in communication with the data storage devices over a second path, the fail-over switches may be used upon detection of a malfunction on one path to switch a controller into connection with the remaining operable path so as to share that path with the other controller.

Abstract: A technique for handling tape back-up data storage systems for use with a data processing system, wherein a single tape driver interface unit has a process controller for controlling access to an array of tape drive units and data storage tapes. Data is transmitted from a host unit to the interface unit via a first small computer system interface (SCSI) bus and is written into first storage regions of the tape via a second SCSI bus and is read from the tape via the second SCSI bus, the interface unit and the first SCSI bus to the host. Parity entries can be determined by the process controller for the data and written into second storage regions of the tapes via the second SCSI bus when operating in a parity mode. Unless a hard error occurs the same data transmitted by the host can be returned from the host.

Abstract: A high frequency signal and a low frequency signal are coupled onto a pair of conductors providing a communication link between two computer components. The high frequency signal may be a differentially coupled Fibre Channel 8B/10B encoded signal. A diplexer includes a low pass filter for attenuating the Fibre Channel signal and a high pass filter for separately attenuating the low frequency signal. A two-way communication link may be provided over twinax cable. An environmental monitor may be in connection with the low frequency communication path.

Abstract: A dynamically upgradeable disk array chassis, and a method for dynamically upgrading a data storage system. The dynamically upgradeable disk array chassis includes a serial bus having a first bus for passing data in one direction and a second bus for passing data in the opposite direction. A shunt connects the first and second buses in a normal state. The shunt has a switched state in which each of the first and second buses is coupled to a separate output from the chassis. The chassis includes an environmental monitor connected to a communication path. Upon connecting a new disk array chassis to an active disk array chassis, the environmental monitor communicates through the communication path before switching the shunt to connect the serial bus with the serial bus of the new disk array chassis.

Abstract: In an array of data storage disks, a data validation system for data arranged in corresponding sectors of a sector group that includes a parity sector. Each user data sector in a sector group is assigned at least two of a plurality of validation fields for placement of a validation stamp. No two data sectors are assigned to identically corresponding sets of validation fields. In the parity sector, there is a parity entry in each of the validation fields created by combining all of the validation stamps in the corresponding validation field throughout the sector group. The validation fields are used to detect partially completed writes into the array of data storage disks.

Abstract: A very fast, memory efficient, highly expandable, highly efficient CCNUMA processing system based on a hardware architecture that minimizes system bus contention, maximizes processing forward progress by maintaining strong ordering and avoiding retries, and implements a full-map directory structure cache coherency protocol. A Cache Coherent Non-Uniform Memory Access (CCNUMA) architecture is implemented in a system comprising a plurality of integrated modules each consisting of a motherboard and two daughterboards. The daughterboards, which plug into the motherboard, each contain two Job Processors (JPs), cache memory, and input/output (I/O) capabilities. Located directly on the motherboard are additional integrated I/O capabilities in the form of two Small Computer System Interfaces (SCSI) and one Local Area Network (LAN) interface. The motherboard includes main memory, a memory controller (MC) and directory DRAMs for cache coherency.

Abstract: A device access controller residing in a first computer system for transferring virtual inputs and outputs representing operations of the first system between the first system and a second system. The device access controller includes a video controller for performing video display operations, a video memory for storing video data representing operations of the first system, a network controller for transferring information between the first system and the second system, a controller processor, and a device access controller bus interconnecting the video controller, the network controller and the processor.

Abstract: A MOSFET, an op-amp, a comparator circuit, and voltage dividers with capacitors are employed in combination to effectuate a soft-start switch with current limiting. The transconductance of the MOSFET is employed so that no sense resistor is required. The MOSFET and op-amp are configured as a closed-loop feedback circuit in which the output of the op-amp is coupled to the gate of the MOSFET and the inverting input of the op-amp is coupled to the output of the soft-start switch via a voltage divider. A first RC circuit provides a voltage to the non-inverting input of the op-amp which can be triggered to gradually rise from a value close to zero to some reference voltage so as to soft-start a load. Current limiting means are effectuated by a comparator circuit and voltage dividers with capacitors.

Abstract: A data processing system and method of operation which substantially reduces the time lost in unnecessarily checking for the presence of all memory references required by a special section of code in an operating system before the program is run and which dynamically protect the program requiring the memory reference from crashing if the memory reference is not presently available. The method assumes that all memory references are available and begins running the special section of code. If a request is made for information not in assigned memory storage, the data processing system interrupts the running of the special section of code and undoes everything the special section of code has done prior to the interrupt. The requested memory reference is then located in storage. The information is retrieved and written into assigned memory. The special section of code is then restarted and supplied the needed information.

Abstract: A security system for a computer system imposes specific limitations on who has access to the computer system and to exactly what operations and data. Viruses are securely contained and prevented from expanding into areas where they can destroy stored programs or data. Viruses are also prevented from being introduced or executed in a large number of instances. The totality of computer functions is broken up into a set of events with an associated set of capabilities and different capabilities are assigned to each user depending on the particular job which that user is to do on the computer system. Also, security labels are placed on each data file and other system resources, and on each process. Further, a range of hierarchy/category labels (MAC labels) is assigned to each process to define a sub-lattice in which special capabilities can apply.

Abstract: A BIOS address decoder for addressing an extended BIOS memory for storing additional microprograms in a computer system. A system component is connected from the bus for receiving program instruction addresses in a first address range and providing corresponding BIOS memory addresses in a corresponding first BIOS address range. The BIOS address decoder includes the system component to receive a first subset of bus address bits representing bus addresses in the first instruction address range and responsive to the first subset of bus address bits to generate corresponding BIOS addresses in the first BIOS address range and a BIOS address indication indicating that the first subset of bus address bits indicates a bus address in the first instruction address range.

Abstract: A support facility for installation of interprocessor unit cabling interconnecting the processor units of a multiple processor unit system in a first network, including a second system for directing the cabling interconnections of the first system and, in each processor unit of the first system, a device access controller connected through a second network to a second system, each device access controller including a memory for storing a unique identifier, and a network controller to interconnect to a network controller of at least one other processor unit. There is a selectably settable anchor bit indicator to indicate a processor unit selected as a first processor unit of the first network, a next connection indicator connected from the device access controller, and connected from the network controller, a transmit test indicator connected from the device access controller and a receive indicator connected from the device access controller.