Abstract: A soft power switch for insertion and removal of a logic unit in a system during continuing operation of the system, including a current switch for each supply voltage to the logic unit that is to be protected, each current switch having a current input connected from a corresponding system power source and a current output connected to the logic unit. The switch includes a gate drive delay connected to each current switch that provides a gate signal controlling the flow of current through each current switch, and a connector having staggered connector pins for sequenced connection of power and control signals as the logic unit is inserted or withdrawn, the soft switch responding to the sequence of control and power signals by controllably and gradually increasing or decreasing the current through the current switches as the logic unit is inserted or withdrawn.

Abstract: A fast tag cache is an array to cache a limited set of identifiers specifying the residency and access rights to memory blocks and cache blocks contained in a node within a distributed memory system built using a cache coherent non-uniform memory access architecture. The purpose of the fast tag array is to ensure peak processor-memory bus throughput each node and minimize the amount of memory required to hold cache state information.

Abstract: Closely related processing threads within a process in a multiprocessor system are collected into thread groups which are globally scheduled as a group based on the thread group structure's priority and scheduling parameters. The thread group structure maintains collective timeslice and CPU accounting for all threads in the group. Within each thread group, each individual thread has a local scheduling priority for scheduling among the threads in its group. The system utilizes a hierarchy of processing levels and run queues to facilitate affining thread groups with processors or groups of processors when possible. The system will tend to balance out the workload among system processors and will migrate threads groups up and down through processing levels to increase cache hits and overall performance. The system is periodically reset to avoid long term unbalanced operation conditions.

Abstract: A multiprocessor cache control uses ping-pong bits to reduces the number of invalidate cycles on a shared system bus in a multiprocessor system with a plurality of caches when data is being updated by multiple CPUs. The ping-pong bit is used predict when sharing is taking place and convert read-shared requests into read-exclusive requests.

Abstract: A MOSFET, an op-amp, a comparator circuit, and voltage dividers with capacitors are employed in combination to effectuate a soft-start switch with current limiting. The transconductance of the MOSFET is employed so that no sense resistor is required. The MOSFET and op-amp are configured as a closed-loop feedback circuit in which the output of the op-amp is coupled to the gate of the MOSFET and the inverting input of the op-amp is coupled to the output of the soft-start switch via a voltage divider. A first RC circuit provides a voltage to the non-inverting input of the op-amp which can be triggered to gradually me from a value close to zero to some reference voltage so as to soft-start a load. Current limiting means are effectuated by a comparator circuit and voltage dividers with capacitors.

Abstract: A battery circuit for use in supplying power to an electronic device comprises a first battery source, a second battery source connected in parallel to the first battery source, a first auxiliary circuit for preventing the first battery source from being charged by the second battery source and for preventing a reverse voltage from being applied by the first battery source to the electronic device and a second auxiliary circuit for preventing the second battery source from being charged by the first battery source and for preventing a reverse voltage from being applied by the second battery source to the electronic device. The first auxiliary circuit includes a first MOSFET which has a first switching state and a second switching state and a first operational amplifier for controlling the switching state of the first MOSFET.

Abstract: A drive regulator circuit board for use with a 3.50 inch disk drive unit. The drive regulator circuit board includes a regulator section for receiving +24 volts distributed power and providing therefrom regulated +5V and +12V DC power, a monitor circuit for monitoring the +5V DC and +12V DC so generated, a SCSI bus reset pulser circuit for generating a SCSI bus reset pulse upon insertion or removal of the drive module, PALS for comparing the local address with an incoming address, control and for turning the DC voltages on or off in response to certain prearranged commands as well as providing SCSI bus activity indication, and a bus for providing SCSI ID information to said 3.50 inch disk drive unit.

Abstract: An expandable memory system and a method for operating a memory system having a variable number of memory banks are described. The memory system can utilize a variable number of separately replaceable memory banks which can be implemented with memory element, such as dynamic random access memory chips, which are of differing speeds and or sizes. The memory system implements an interleaving of memory addresses among the memory banks as a function of the number of banks actually present so that successive memory accesses are not unnecessarily delayed by the recovery times of the memory elements. The memory system includes a programmable address decoder having a writable memory which provides bank address signals. Each of the banks includes a respective delay line for providing an output signal a respective presettable time after address signals are received by that bank for signalling to the host that data is ready to be transferred.

Abstract: A shared-disk cluster system includes a cluster membership manager framework which coordinates the joining or leaving among all nodes in a cluster including taking the multiple layers of involved subsystems through transitions. Subsystems are notified of transitions in particular order depending upon the transition, and all nodes' subsystems receiving a notification must process that notification prior to another layer of subsystems being notified. One of the subsystems registered for notification is an event manager in user space. The event manager carries out transfers of client services, including user applications, resulting from nodes joining and leaving the cluster. This includes a registration and launch service which registers a node, or multiple nodes, in a cluster which claims, or is assigned, responsibility for the service and provides an optional launching function which initiates the client service upon successful registration.

Abstract: The time lost in unnecessarily checking for the presence of all memory references required by a special section of code in an operating system before the program is run and which dynamically protects the program requiring the memory reference from crashing if the memory reference is not presently available is substantially reduced. The method assumes that all memory references are available and begins running the special section of code. If a request is made for information not in assigned memory storage, the data processing system interrupts the running of the special section of code and undoes everything the special section of code has done prior to the interrupt. The requested memory reference is then located in storage. The information is retrieved and written into assigned memory. The special section of code is then restarted and supplied the needed information.

Abstract: A method and apparatus for backing up files from a logical disk are described to a backup tape and restoring all or part of the files to the logical disk. Separate "backup" and "copy" buffers in the host processor's main memory are employed during a backup operation. Backup buffers hold data read from the logical disk during the sequential backup operation. Copy buffers hold data read from the logical disk prior to execution of a write operation to a portion of the disk not yet backed up. Data is stored on the backup tape in logical tape records containing either backup data or copied data. A full restoration of all files can be done in one read of the backup tape. A partial restoration of selected files can be done in two reads of the backup tape.

Abstract: A disk drive module adapted for use in a data processing system, the system including first and second disk drive module guide plates. The disk drive module comprises an elongated, generally rectangular frame. The top wall of the frame includes a fin slidably insertable into a groove formed on the second guide plate, and the bottom wall of the frame includes a T-bar slidably insertable into a channel formed on the first guide plate. The T-bar includes a detent which releasably engages a pawl formed in the channel for securing the T-bar within the channel. A 3.5 inch disk drive and a regulator card are mounted within the frame. The regulator card is mounted on the frame for movement in three directions using bifurcated squeezable snaps inserted through oversized holes formed in the regulator card. Each snap includes a tab which limits upward movement of the card.

Abstract: A technique for permitting data transfers between a high speed bus and a low speed bus which operate independently and asynchronously wherein when the low speed bus requires access to the high speed bus, the busy status of the latter bus is determined and transfers are made to the high speed bus at high speed when such bus is not busy. When the high speed bus requires access to the low speed bus, if the low speed bus is busy the requesting master on the high speed bus is temporarily placed in a pending status and is removed from its tenure on the high speed bus, so that the high speed bus is free to handle other requests. When the low speed bus is free, the highest priority pending requestor is provided access to the low speed bus on a priority basis over all then current requestors.

Abstract: A method for handling data in a plurality of data storage disks having user data sectors and corresponding parity sectors, the method being used when the disks are being operated in a non-degraded or a degraded mode wherein a non-volatile RAM is used in an array control processor which controls the operation of such disks. When new data is to be written into the array, the non-volatile RAM stores information identifying the array, the starting sector into which data is to be written and the number of sectors to be used for writing the new data so that parity and data entries in corresponding sectors can be matched when a power failure occurs. Further, when opening a new array, the data and parity entries in corresponding sectors can be matched and verified, the operation for such matching being performed in between other operations that are being performed by the control processors (i.e., in the "background" thereof).

Abstract: A method for handling attempts by multiple processing threads to access a shared system resource is disclosed. When a thread attempts to access a locked resource, the thread creates a description of the operation it intended to perform and stores the description on a deferred operation list associated with that resource. The deferred operation list is monitored by the thread which has control of the resource. If one or more entries is detected, the entries are removed from the list and processed by the controlling thread.

Abstract: A technique for generating gated clock signals for use in enabling various operating gating units in a data processing system in which an internal reference clock signal is used to generate both processor clock signals and the gated clock signals such that the latter signals are substantially synchronous with the processor clock signals. D-flip-flop circuitry together with a delay unit having an adjustable time delay are used to generate a gated clock signal. The overall time delay, from the time of which the circuitry is enabled until the gated clock signal is produced, is appropriately set by selecting the required time delay so that the overall time delay is essentially the same as the time delay required to generate the processor clock signals. Accordingly, the edges of the gated clock signals can be made to coincide with the edges of the processor clock signals.

Abstract: A method for performing address and data transfers among a plurality of different units of a data processing system having a system bus which includes an address bus and a data bus. The system uses arbitration phase, address transfer phase, and data transfer phase operations which require the use of unique handshake signals at each phase so as to permit address and data transfers to occur on a suitable priority basis with respect to different ones of such units in a pipelined manner using non-multiplexed, asynchronous operations.

Abstract: In a network communication system passing messages between gateways via a message handling system the gateways are interfaced specifically to their respective network access units and are interfaced generically to the message handling system using routines common to all gateways. Messages are sent in protocol data units including recipient addresses which do not identify recipient gateways as such; the gateways are used transparently. The data format is CCITT 1988 X400 standard with automatic conversion to and from this format at sending and receiving gateways plus automatic document conversion. Message handling involves waiting for many services and events. The invention allows calling routines to avoid pending while waiting for events and services. Service routines, including event watching and timer routines, schedule notifications on to queues and the main processing task runs notifications off the queues by calling a run routine.

Abstract: An interface system for transmitting a pulse waveform signal between a host computer and a plurality of peripheral units wherein such signal is transmitted on a dedicated bus, the peripheral units being connected to the bus in selected groups thereof. Each group has a buffer unit connected between the group of units and the host unit, the buffer unit including circuitry for providing signal transmission in only one direction, for controlling the final signal level of the signal, and for controlling the slope of the trailing edge of the signal so that signal degradation is minimized.

Abstract: A bus arbitration algorithm using round robin and variable packet counts. In addition, each node is assigned a maximum packet size which can be adjusted by the operating system. The round robin determines which node will be granted the bus based on priority on a serial wrap-around list. The packet count is one factor in determining how long the node granted the bus may use it. The maximum packet size is a second factor in determining the permitted duration on the bus.