Abstract: A source driver includes a digital-to-analog converter configured to receive a data signal, convert the received data signal into an analog signal, and output the analog signal, an output unit including amplifiers configured to amplify the analog signal, a control signal provision unit configured to output at least one control signal based on or in response to a first bias signal, at least one level shifter configured to shift a level of the control signal(s) based on or in response to a second bias signal having a higher voltage than the first bias signal and output at least one level-shifted control signal, and a protector configured to detect a voltage of the first bias signal and turn off the amplifiers and the level shifter when the detected voltage of the first bias signal is less than a predetermined reference voltage.

Abstract: A backside illuminated image sensor includes pixel regions disposed in a substrate, an insulating layer disposed on a frontside surface of the substrate, a bonding pad disposed on a frontside surface of the insulating layer, and an anti-reflective layer disposed on a backside surface of the substrate. The substrate has a first opening for partially exposing a backside surface of the insulating layer, and the insulating layer has a third opening for partially exposing a backside surface of the bonding pad. The anti-reflective layer comprises a first portion disposed on an inner side surface of the first opening and a second portion disposed on a portion of the backside surface of the insulating layer exposed by the first opening and having a second opening connecting the first opening with the third opening, and a first spacer is disposed on inner side surfaces of the second opening and the third opening.

Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes a first body region disposed in a substrate and having a first conductivity type, a second body region disposed on the first body region and having the first conductivity type and a portion protruding in a channel length direction, a source region disposed in the second body region and having a second conductivity type, a drain region spaced apart from the protruding portion of the second body region in the channel length direction and having the second conductivity type, a well region configured to electrically connect the protruding portion of the second body region and the drain region and having the second conductivity type, and a gate structure disposed on the protruding portion of the second body region.

Abstract: A half-power buffer amplifier is disclosed. The amplifier includes an amplification unit configured to differentially amplify differential input signals, the amplification unit including nodes configured to output differentially amplified first to fourth output signals, a first output buffer unit including first and second transistors, and an output node to which the first and second transistors are connected, a second output buffer unit including third and fourth transistors, wherein the third and fourth transistors are connected to the output node, a first control switch between the first output node and the second transistor and controlled by a polarity control signal, and a second control switch between the second output node and the third transistor and controlled by a complement of the polarity control signal.

Abstract: An output buffer circuit is disclosed to achieve a high slew rate without increasing current consumption. The output buffer circuit includes an input circuit configured to output a first signal and a second signal in response to an input signal, and a slew rate control circuit configured to connect one of the first signal and the second signal to an output terminal to control a slew rate of an output signal based on or in response to a potential difference between the input signal and the output signal.

Abstract: An ESD protection SCR device includes an epitaxial layer provided on a P-type semiconductor substrate, the epitaxial layer having the P-type conductivity, element isolation layers provided on the epitaxial layer, the element isolation layers dividing the epitaxial layer into an anode region and a cathode region, a first well of an N-type conductivity, provided in a portion of the epitaxial layer corresponding to the anode region, a first impurity region provided on a surface of the first well, the first impurity region being connected to an anode terminal and having a high concentration P-type conductivity, a second well of the P-type conductivity, provided in a portion of the epitaxial layer corresponding to the cathode region, a second impurity region provided on a surface of the second well, the second impurity region being connected to a cathode terminal and having a high concentration N-type conductivity, and a floating well of the N-type conductivity, buried in the epitaxial layer.

Abstract: A non-volatile memory array includes gate structures disposed on a substrate, each of the gate structures including a tunneling oxide layer positioned on the substrate, a floating gate positioned on the tunneling oxide layer and being arranged along a first direction on the tunneling oxide layer, sidewall gates disposed on sidewalls of the floating gate, extending in the first direction and being spaced apart from each other, and a gate dielectric layer interposed between the floating gate and the sidewall gates, bit lines disposed over the substrate, each extending in a second direction to intersect the sidewall gates, a drain region positioned in an upper portion of the substrate, the drain region overlapping, and being electrically connected to, the one of the bit lines, and a source line positioned between adjacent sidewall gates, the source line extending in the first direction and being buried in the substrate.

Abstract: A MEMS microphone includes a cavity extending portion that increases the size of the cavity. The cavity extending portion can be sloped or stepped in order to create a desired profile of the extended cavity shape. Thus, the volume of the cavity may be increased in order to decrease the compliance and to increase a Signal to Noise Ratio.

Abstract: A MEMS microphone includes a substrate defining a cavity, a diaphragm being spaced apart from the substrate, covering the cavity, and configured to generate a displacement of the diaphragm in response to an applied acoustic pressure, an anchor extending from an end portion of the diaphragm, and fixed to an upper surface of the substrate to support the diaphragm and a back plate disposed over the diaphragm, the back plate being spaced apart from the diaphragm such that an air gap is maintained between the back plate and the diaphragm, and defining a plurality of acoustic holes, wherein the anchor has a repetitive concave-convex shape in a direction toward a center of the diaphragm so that the anchor acts as a resistance to an acoustic wave.

Abstract: A lateral double diffused MOS transistor includes a drain region positioned in a central region of an upper surface portion of an epitaxial layer, the drain region including a first well of a second conductive type, a source region positioned in the upper surface portion of the epitaxial layer and spaced apart from the drain region, the source region having a ring shape to surround the drain region and including a second well of the first conductive type, a first gate electrode disposed on the epitaxial layer and between the drain region and the source region, a P-sub region disposed on an upper surface of the epitaxial layer and laterally spaced apart from the source region, and a deep well of the second conductive type, disposed in the epitaxial layer, the deep well radially extending from the first well through the second well to entirely surround the drain region and the source region.

Abstract: An element isolation structure includes a substrate defining a trench including an upper trench and a lower trench in communication with each other, the substrate including an inclined sidewall that forms the upper and lower trench; a first thin film liner on the substrate and conforming to the substrate, the first thin film liner having a substantially uniform thickness trench; a second thin film liner pattern selectively on a lower portion of the first thin film liner within a volume defined by the lower trench, the second thin film liner pattern having a substantially uniform thickness; a lower isolation layer formed on the second thin film liner pattern and substantially filling the volume defined by the lower trench; and an upper isolation layer formed on an upper portion of the first thin film liner and the lower isolation layer and substantially filling a volume defined by the upper trench.

Abstract: A MEMS microphone includes a substrate having a cavity, a back plate disposed over the substrate, a diaphragm disposed between the substrate and the back plate, a first supporting member surrounding the diaphragm, the first supporting member including first dam portions arranged along a circumference of the diaphragm, and first slit portions between the first dam portion adjacent to each other to be configured to support the diaphragm from a lower face of the substrate, and a second supporting member surrounding the first supporting member, the second supporting member including second dam portions arranged along a circumference of the first dam portions, and second slit portions between the second dam portion adjacent to each other to be configured to further support the diaphragm from the lower face of the substrate. Thus, the MEMS microphone has an increased acoustic resistance.

Abstract: A MEMS microphone includes a substrate having a cavity, a back plate disposed over the substrate to cover the cavity and having a plurality of acoustic holes, a diaphragm disposed over the substrate to cover the cavity, the diaphragm being disposed under the back plate, including a venting hole communicating with the cavity, and sensing an acoustic pressure to create a displacement, and a first insulation layer interposed between the substrate and the diaphragm to support an end portion of the diaphragm to separate the diaphragm from the substrate, and the first insulation layer having an opening formed at a position corresponding to the cavity to expose the diaphragm. Thus, since the process of forming an anchor may be omitted, the process may be simplified, and process time may be shortened.

Abstract: A display driver integrated circuit (DDI) includes a level shifter unit configured to convert a level of a control signal to a voltage in a range that equal to or greater than a first voltage and is equal to or less than a second voltage and output a switch control signal, and a voltage generator including a capacitor and a switch that is turned on or off based on or in response to the switch control signal and configured to generate at least one third voltage.

Abstract: An anode cell array unit for an organic light emitting diode display. The anode cell array unit is disposed on a substrate structure unit including an active element for each pixel, and has an organic light emitting unit is disposed thereon.

Abstract: Disclosed is a gamma correction circuit and method capable of minimizing power consumption by adding third and fourth input amplifiers receiving reference voltages which are identical to voltages to first and second input amplifiers, respectively, and deactivating the first and second input amplifiers during an always on display (AOD) mode. The gamma correction circuit includes a first input amplifier configured to output a maximum voltage when active, a second input amplifier configured to output a minimum voltage when active, a third input amplifier configured to output a highest gamma voltage in response to the first reference voltage, and a fourth input amplifier configured to output a lowest gamma voltage in response to the second reference voltage. The first and second input amplifiers are deactivated when the display driving device operates in the AOD mode.

Abstract: Disclosed is a high voltage semiconductor device and a method of manufacturing the same.

Abstract: A method of manufacturing a gate structure for a nonvolatile memory device is disclosed. A tunneling oxide layer is formed on a substrate, and then a first polysilicon layer, a gate dielectric layer, a second polysilicon layer and a hard mask pattern are sequentially formed on the tunneling oxide layer. Then, the second polysilicon layer, the gate dielectric layer, and the first polysilicon layer are patterned through an etching process using the hard mask pattern to form stacked memory gates on the tunnel oxide layer, each including a floating gate, a gate dielectric layer pattern and a control gate on the tunneling oxide layer, and a select gate provided between the memory gates on the tunneling oxide layer.

Abstract: An anode structure of an organic light emitting diode display device, includes an insulating interlayer disposed on a silicon substrate, a first metal layer pattern disposed on the insulating interlayer comprising a first metal to be configured to upwardly reflect light, a second metal layer pattern formed on the first metal layer pattern comprising a second metal having a work function of 4.0 eV or more, and a diffusion barrier layer pattern interposed between the first metal layer pattern and the second metal layer pattern for preventing elements of the first metal or the second metal from diffusing between the first metal layer and the second metal layer.

Abstract: A high voltage power diode includes a P-type semiconductor substrate, a P-type epitaxial layer provided on the semiconductor substrate, an N-type isolation layer provided at a lower portion of the epitaxial layer, the isolation layer extending in a horizontal direction, oxide isolation layer provided at an upper surface of the epitaxial layer, the oxide isolation layer defining the epitaxial layer into an anode region and a cathode region, an first well of N-type conductivity, and a second well of P-type conductivity are provided on the upper surface of the epitaxial layer, a guard ring structure provided on the upper surface of the epitaxial layer and spaced apart from the second well in a horizontal direction, the guard ring structure including a third well having a first sub-well of N-type conductivity, a second sub-well of P-type conductivity and an third sub-well of N-type conductivity which are arranged in a horizontal direction, and a guard ring terminal electrically connected to the anode terminal.