Abstract: An image sensor includes a charge accumulation region disposed in a substrate and having a first conductivity type, a charge storage region disposed in the substrate to be spaced apart from the charge accumulation region and having the first conductivity type, a transfer gate electrode disposed on a channel region between the charge accumulation region and the charge storage region to transfer a charge from the charge accumulation region to the charge storage region, and a well region having a second conductivity type and disposed below the charge storage region to inhibit a charge generated below the charge storage region from being moved to the charge storage region.

Abstract: A semiconductor integrated circuit device comprising: a substrate; a buried layer disposed on one side of the substrate; a well including a semiconductor region disposed on one side of the buried layer; and a Schottky diode portion disposed on one side of the well, wherein the Schottky diode portion comprises an anode, a guard ring electrically connected with the anode, and a poly field plate electrically connected with the anode and the guard ring, and the guard ring comprises at least one slit configured to block a flow of current.

Abstract: Proposed is an indirect Time-of-Flight (ToF) structure. In the indirect ToF structure, an electric charge storage portion in which electric charge is temporarily stored is provided between a photoelectric conversion portion and a floating diffusion portion, thereby making it possible to perform Correlated Double Sampling (CDS) and to remove noise during readout after an integration time.

Abstract: A pillar structure of a super junction semiconductor device includes a semiconductor layer having a first conductivity type and pillars having a second conductivity type. The semiconductor layer includes an active region and a peripheral region surrounding the active region. The pillars extend in a vertical direction within the semiconductor layer and extend in a horizontal direction across the active region and the peripheral region. Each of the pillars includes an active pillar disposed within the active region, a lower peripheral pillar disposed within the peripheral region and connected to the active pillar, and a pair of upper peripheral pillars disposed on the lower peripheral pillar and branching from the active pillar.

Abstract: Disclosed is a high voltage semiconductor device and a method of manufacturing the same and, more particularly, to a high voltage semiconductor device and a method of manufacturing the same that enables an improvement in the breakdown voltage relative to the on-resistance by forming a top region in or at the surface of the substrate when the device includes a field plate adjacent to a gate electrode.

Abstract: A semiconductor device comprising: a substrate, an active cell region comprising a first active region including a recessed region and a second active region on the substrate, an edge terminal region surrounding the active cell region on the substrate, a first peripheral region comprising a first region within the recessed region and a second region disposed between the first active region and the edge terminal region on the substrate, a second peripheral region disposed between the second active region and the edge terminal region, and a first body diode region extending from the second region of the first peripheral region to a portion of the first active region.

Abstract: A semiconductor device is provided.

Abstract: A superjunction semiconductor device with an epitaxial layer having different effective thicknesses and a method of manufacturing the same are disclosed. The superjunction semiconductor device includes an epitaxial layer having different thicknesses in a cell region and a ring region to decrease a breakdown voltage of the cell region relative to a breakdown voltage of the ring region so as to reveal a characteristic of the breakdown voltage of the cell region.

Abstract: Disclosed is a superjunction semiconductor device (1) and a method for manufacturing the same and, more particularly, to a superjunction semiconductor device (1) and a method for manufacturing the same seeking to improve breakdown voltage characteristics of the device by effectively dispersing a lateral electric field in a ring region R in the lower portion of an epitaxial layer by forming first conductivity type floating impurity-doped regions in the lower portion of the epitaxial layer in the ring region R under a p-rich condition.

Abstract: A semiconductor device comprising: a substrate; a high side region on the substrate, a drift region surrounding the high side region; an insulating region between the high side region and the drift region, and a first conductive pattern disposed in the insulating region and surrounding the high side region.

Abstract: Disclosed are a SPAD pixel structure and a method of manufacturing the same, in which a cathode contact is formed on a back surface of a substrate instead of a front surface, thereby reducing or minimizing the distance between adjacent unit pixels and increasing the fill-factor of each unit pixel.

Abstract: A superjunction semiconductor device having a reduced source area and a method of manufacturing the same and, more particularly, to a semiconductor device and a method of manufacturing the same, in which the semiconductor device realizes a reduction in the area of a source in a body region to reduce the current during a short circuit fault, thus delaying a temperature increase and increasing the time before temperature-related device destruction.

Abstract: A semiconductor device is provided. The semiconductor device comprises: a substrate including an active region having an active cell region and a termination region surrounding the active region; a gate bus disposed in the active region to be non-overlapped with the active cell region; a gate electrode extending from the gate bus and disposed in the active cell region; a source region disposed on at least one side of the gate electrode in the active cell region; a gate insulating layer disposed between the gate bus and the substrate and between the gate electrode and the substrate; a gate metal disposed on the gate bus to be connected to the gate bus; and a source metal disposed on the gate electrode to be connected to the source region, wherein the gate bus and the gate electrode are disposed on the same layer.

Abstract: A resonator drive method is provided. The resonator drive method comprises: driving a third electrode that is higher than the first electrode and the second electrode based on an upper surface of the substrate, which are spaced apart from each other at a first interval on a substrate, to descend toward the substrate; and arranging the third electrode between the first electrode and the second electrode to be in contact with the upper surface of the substrate and arranging the first electrode, the second electrode, and the third electrode to be spaced apart from one another at a second interval, wherein the second interval is less than the first interval.

Abstract: Disclosed is a low-voltage detection floating N-well bias circuit. The circuit includes a power detector configured to detect states of first power (VDD) and second power (DVDD) at different power levels; a switch configured to perform a switching operation according to the states of the first power (VDD) and the second power (DVDD); and a voltage output circuit configured to output the first power (VDD) or the second power (DVDD) as an N-well bias voltage according to the states of the first power (VDD) and the second power (DVDD) and the switching operation of the switch. Accordingly, when the first power (VDD) and the second power (DVDD) are supplied and the second power (DVDD) has a low voltage state, the floating N-well bias circuit can continuously bias an N-well with the second power (DVDD), without dropping the second power (DVDD).

Abstract: Disclosed is a semiconductor device and a method for manufacturing the same and, more particularly, a semiconductor device and a method for manufacturing the same seeking to improve on-resistance and breakdown voltage characteristics compared to existing semiconductor structures by forming an air gap under a gate field plate adjacent to a gate electrode or over a drift region of the semiconductor device.

Abstract: An input/output circuit for a memory and a method of controlling the same are disclosed. The input/output circuit and the method of controlling the same are configured to prevent a memory element from being falsely or incorrectly programmed due to an ESD pulse. More particularly, the input/output circuit and the method of controlling the same include an ESD detection unit configured to detect a programming voltage or an ESD pulse on a pad terminal, a control logic unit configured to transmit a first voltage or a second voltage according to the programming voltage and the ESD pulse, and a switch unit configured to perform a turn-on or turn-off operation according to the first voltage or the second voltage.

Abstract: A display driver integrated circuit comprising an operational amplifier configured to amplify an input voltage and generate an output voltage and a slew rate control circuit configured to generate a compensation current based on a difference between the input voltage and the output voltage and provide the generated compensation current to the operational amplifier, wherein the slew rate control circuit comprises a comparison circuit configured to compare the input voltage and the output voltage and generate a difference current corresponding to a difference between the input voltage and the output voltage, a pull-down circuit comprising a pull-down transistor group and configured to generate a pull-down compensation current by current-mirroring the generated difference current, and a pull-up circuit comprising a pull-up transistor group and configured to generate a pull-up compensation current by current-mirroring the generated difference current is provided.

Abstract: Disclosed is a high voltage semiconductor device. More particularly, the present disclosure relates to a semiconductor device capable of improving the breakdown voltage characteristics in an off-state and in an on-state by electrically connecting a first source metal to a source in a core region and in corner regions.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a first region and a second region surrounding the first region, a collector extending in a first direction in the first region of the substrate, an emitter that is spaced apart from the collector in a second direction and extends in the first direction, in the first region of the substrate, a floating region that is disposed between the collector and the emitter and extends in the first direction, in the first region of the substrate, a first device separation region between the floating region and the collector in the first region of the substrate, a second device separation region between the floating region and the emitter in the first region of the substrate and a base disposed in the second region of the substrate, wherein the floating region is not connected to an element including a conductor.