Abstract: A semiconductor device is provided.

Abstract: Disclosed is a superjunction semiconductor device (1) and a method for manufacturing the same and, more particularly, to a superjunction semiconductor device (1) and a method for manufacturing the same seeking to improve breakdown voltage characteristics of the device by effectively dispersing a lateral electric field in a ring region R in the lower portion of an epitaxial layer by forming first conductivity type floating impurity-doped regions in the lower portion of the epitaxial layer in the ring region R under a p-rich condition.

Abstract: A superjunction semiconductor device with an epitaxial layer having different effective thicknesses and a method of manufacturing the same are disclosed. The superjunction semiconductor device includes an epitaxial layer having different thicknesses in a cell region and a ring region to decrease a breakdown voltage of the cell region relative to a breakdown voltage of the ring region so as to reveal a characteristic of the breakdown voltage of the cell region.

Abstract: A semiconductor device comprising: a substrate; a high side region on the substrate, a drift region surrounding the high side region; an insulating region between the high side region and the drift region, and a first conductive pattern disposed in the insulating region and surrounding the high side region.

Abstract: Disclosed are a SPAD pixel structure and a method of manufacturing the same, in which a cathode contact is formed on a back surface of a substrate instead of a front surface, thereby reducing or minimizing the distance between adjacent unit pixels and increasing the fill-factor of each unit pixel.

Abstract: A superjunction semiconductor device having a reduced source area and a method of manufacturing the same and, more particularly, to a semiconductor device and a method of manufacturing the same, in which the semiconductor device realizes a reduction in the area of a source in a body region to reduce the current during a short circuit fault, thus delaying a temperature increase and increasing the time before temperature-related device destruction.

Abstract: A semiconductor device is provided. The semiconductor device comprises: a substrate including an active region having an active cell region and a termination region surrounding the active region; a gate bus disposed in the active region to be non-overlapped with the active cell region; a gate electrode extending from the gate bus and disposed in the active cell region; a source region disposed on at least one side of the gate electrode in the active cell region; a gate insulating layer disposed between the gate bus and the substrate and between the gate electrode and the substrate; a gate metal disposed on the gate bus to be connected to the gate bus; and a source metal disposed on the gate electrode to be connected to the source region, wherein the gate bus and the gate electrode are disposed on the same layer.

Abstract: A resonator drive method is provided. The resonator drive method comprises: driving a third electrode that is higher than the first electrode and the second electrode based on an upper surface of the substrate, which are spaced apart from each other at a first interval on a substrate, to descend toward the substrate; and arranging the third electrode between the first electrode and the second electrode to be in contact with the upper surface of the substrate and arranging the first electrode, the second electrode, and the third electrode to be spaced apart from one another at a second interval, wherein the second interval is less than the first interval.

Abstract: Disclosed is a low-voltage detection floating N-well bias circuit. The circuit includes a power detector configured to detect states of first power (VDD) and second power (DVDD) at different power levels; a switch configured to perform a switching operation according to the states of the first power (VDD) and the second power (DVDD); and a voltage output circuit configured to output the first power (VDD) or the second power (DVDD) as an N-well bias voltage according to the states of the first power (VDD) and the second power (DVDD) and the switching operation of the switch. Accordingly, when the first power (VDD) and the second power (DVDD) are supplied and the second power (DVDD) has a low voltage state, the floating N-well bias circuit can continuously bias an N-well with the second power (DVDD), without dropping the second power (DVDD).

Abstract: Disclosed is a semiconductor device and a method for manufacturing the same and, more particularly, a semiconductor device and a method for manufacturing the same seeking to improve on-resistance and breakdown voltage characteristics compared to existing semiconductor structures by forming an air gap under a gate field plate adjacent to a gate electrode or over a drift region of the semiconductor device.

Abstract: An input/output circuit for a memory and a method of controlling the same are disclosed. The input/output circuit and the method of controlling the same are configured to prevent a memory element from being falsely or incorrectly programmed due to an ESD pulse. More particularly, the input/output circuit and the method of controlling the same include an ESD detection unit configured to detect a programming voltage or an ESD pulse on a pad terminal, a control logic unit configured to transmit a first voltage or a second voltage according to the programming voltage and the ESD pulse, and a switch unit configured to perform a turn-on or turn-off operation according to the first voltage or the second voltage.

Abstract: A display driver integrated circuit comprising an operational amplifier configured to amplify an input voltage and generate an output voltage and a slew rate control circuit configured to generate a compensation current based on a difference between the input voltage and the output voltage and provide the generated compensation current to the operational amplifier, wherein the slew rate control circuit comprises a comparison circuit configured to compare the input voltage and the output voltage and generate a difference current corresponding to a difference between the input voltage and the output voltage, a pull-down circuit comprising a pull-down transistor group and configured to generate a pull-down compensation current by current-mirroring the generated difference current, and a pull-up circuit comprising a pull-up transistor group and configured to generate a pull-up compensation current by current-mirroring the generated difference current is provided.

Abstract: Disclosed is a high voltage semiconductor device. More particularly, the present disclosure relates to a semiconductor device capable of improving the breakdown voltage characteristics in an off-state and in an on-state by electrically connecting a first source metal to a source in a core region and in corner regions.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a first region and a second region surrounding the first region, a collector extending in a first direction in the first region of the substrate, an emitter that is spaced apart from the collector in a second direction and extends in the first direction, in the first region of the substrate, a floating region that is disposed between the collector and the emitter and extends in the first direction, in the first region of the substrate, a first device separation region between the floating region and the collector in the first region of the substrate, a second device separation region between the floating region and the emitter in the first region of the substrate and a base disposed in the second region of the substrate, wherein the floating region is not connected to an element including a conductor.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including first and second regions and a third region between the first and second regions, a first gate electrode of a first transistor extending along a first direction on the third region, a second gate electrode of a second transistor spaced apart from the first gate electrode in a second direction on the third region and extending along the first direction, a first common region extending from the third region to the first region and disposed between the first gate electrode and the second gate electrode, a first body region extending from the third region to the first region and disposed below the second gate electrode, a first insulating portion between the first common region and the first body region in the first region and a connection region connecting the first common region and the first body region.

Abstract: A backside illuminated image sensor and a method of manufacturing the same are disclosed. The backside illuminated image sensor includes a substrate having a frontside surface and a backside surface, pixel regions disposed in the substrate, an insulating layer disposed on the frontside surface of the substrate, a bonding pad disposed on a frontside surface of the insulating layer, a second bonding pad connected to a backside surface of the bonding pad through the substrate and the insulating layer and exposed through the backside surface of the substrate, and a test pad connected to the backside surface of the bonding pad through the substrate and the insulating layer, exposed through the backside surface of the substrate, and for testing whether the second bonding pad is normally connected to the backside surface of the bonding pad.

Abstract: Disclosed are a superjunction semiconductor device and a method of manufacturing the same. More particularly, the present disclosure relates to a superjunction semiconductor device and a method of manufacturing the same, in which the device includes a field oxide layer having an uppermost end or surface that is higher than that of a gate oxide layer, between a gate electrode and a second pillar region in a cell region. This enables a reduction in gate-drain parasitic capacitance, thereby increasing switching speed and reducing switching loss.

Abstract: A super junction semiconductor device includes a substrate of a first conductive type, the substrate including an active region, a peripheral region surrounding the active region and a transition region interposed between the active region and the peripheral region, an epitaxial layer disposed on the substrate, the epitaxial layer having a the first conductive type, a plurality of pillars extending in a vertical direction and arranged within the epitaxial layer, gate structures disposed on the epitaxial layer in both the active region and the transition region, and the each of the gate structures extending across the epitaxial layer and the pillars in a horizontal direction, and a reverse recovery layer of a second conductive type, the reverse recovery layer having a vertical formation heights different as between on the pillars and on the epitaxial layer, the reverse recovery layer configured to dissipate a reverse recovery current in the transition layer.

Abstract: A backside illuminated image sensor and a method of manufacturing the same are disclosed. The backside illuminated image sensor includes a substrate having a frontside surface, a backside surface and a recess formed in a backside surface portion thereof, pixel regions disposed in the substrate, an insulating layer disposed on the frontside surface of the substrate, a bonding pad disposed on a frontside surface of the insulating layer, a second bonding pad formed with a constant thickness on a bottom surface and an inner side surface of the recess to form a second recess in the recess and electrically connected with the bonding pad, and a third bonding pad formed in the second recess to fill the second recess.

Abstract: Disclosed is an amplifier capable of minimizing shortcircuit current of an output stage of a buffer upon transition of an output voltage while having a high slew rate without increasing power consumption. The amplifier includes an input unit, a conversion unit, an amplification unit, a frequency compensation circuit, and a short-circuit current minimization circuit. Alternatively, the amplifier includes an input unit, a conversion unit, an amplification unit, a frequency compensation circuit, a short-circuit current minimization circuit, and a slew rate improvement circuit.