Patents Assigned to Development Limited
  • Patent number: 12182059
    Abstract: The present disclosure relates to a secondary device comprising a first port receiving a clock signal from a first port of a primary device and a second port connected to a second port of the primary device. The clock signal determines, for each bit transmission, first, second, third and fourth successive phases. The secondary device puts its second port in a high impedance state during the first, second and fourth phases of each bit transmission. During the third phase of each transmission of a bit of data from the secondary device to the primary device, the secondary device discharges its second port when the transmitted bit has a first value and leaves its second port in a high impedance state when the transmitted bit has a second value.
    Type: Grant
    Filed: December 8, 2022
    Date of Patent: December 31, 2024
    Assignee: STMicroelectronics (Research & Development) Limited
    Inventors: Jeffrey M. Raynor, Sergio Miguez Aparicio, Benjamin Thomas Sarachi
  • Patent number: 12178851
    Abstract: The present invention relates to methods of treating disease states, including cancer, in a human comprising systemically administering a STING agonist, or a pharmaceutically acceptable salt thereof, to said human.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: December 31, 2024
    Assignee: GlaxoSmithKline Intellectual Property Development Limited
    Inventors: George Scott Pesiridis, Jean-Luc Tran, Jingsong Yang, Joshi M Ramanjulu
  • Publication number: 20240425581
    Abstract: Provided herein are interleukin 7 (IL-7) binding proteins, pharmaceutical compositions and their use in the treatment or prevention of a disease or condition.
    Type: Application
    Filed: September 3, 2024
    Publication date: December 26, 2024
    Applicant: GlaxoSmithKline Intellectual Property Development Limited
    Inventors: Gerben BOUMA, Edward Thomas COULSTOCK, David DIXON, Stephanie HOPLEY, Alan Peter LEWIS, Jessica Lynn NEISEN
  • Patent number: 12167142
    Abstract: In an embodiment an apparatus includes a scanning photographic sensor configured to acquire an image, according to an integration time of the sensor, of a scene illuminated with periodically emitted light pulses by a source, so that the image has a regular succession of bands with different luminosities when the integration time of the sensor is different from a period of the light pulses, a processor configured to generate a signature vector representative of the regular succession of bands with different luminosities being present in the image acquired by the photographic sensor, wherein the signature vector is independent of a reflectance of an objects of the scene and of a level of light in the scene, determine a frequency of the bands in the image on basis of the generated signature vector and determine the period of the pulses of the source on basis of the determined frequency of the bands in the image, and a controller configured to adjust the integration time of the photographic sensor so that the int
    Type: Grant
    Filed: June 24, 2022
    Date of Patent: December 10, 2024
    Assignees: STMicroelectronics (Research & Development) Limited, STMicroelectronics France
    Inventors: Arnaud Bourge, Tanguy Le Dauphin, Antoine Drouot, Brian Douglas Stewart
  • Publication number: 20240375951
    Abstract: An energy provision system for and a method of operating a building or a system of buildings are described. Hydrocarbons from a hydrocarbon input are processed to produce a hydrogen gas output and a carbon solids output. The hydrogen gas output is provided to one or more hydrogen gas consumers for providing heating or power to the building or system of buildings. The carbon solids output is provided to a waste water system for removing contaminants or pollutants from waste water.
    Type: Application
    Filed: August 30, 2022
    Publication date: November 14, 2024
    Applicant: HiiROC-X Developments Limited
    Inventor: Ate Wiekamp
  • Publication number: 20240379891
    Abstract: A single photon avalanche diode (SPAD) pixel circuit includes a SPAD, a clamping transistor coupled to the anode of the SPAD, and readout circuitry. The clamping transistor limits the anode voltage to a threshold below the readout circuitry's maximum operating voltage. In one embodiment, quenching and enabling transistors are implemented using single-layer gate oxide technology, while the clamping transistor uses extended drain technology. A regulation circuit generates a voltage clamp control signal for an array of pixels. Another embodiment utilizes a stacked chip design with the SPAD and a cathode-side quenching element on one chip, and the clamping transistor and readout circuitry on another. This incorporates a parasitic capacitance from deep trench isolation. Additional biasing transistors may be used for fine-tuning the clamped anode voltage.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Applicant: STMicroelectronics (Research & Development) Limited
    Inventors: Mohammed AL-RAWHANI, Neale DUTTON, John Kevin MOORE, Bruce RAE, Elsa LACOMBE
  • Patent number: 12143719
    Abstract: A method includes dividing a field of view into a plurality of zones and sampling the field of view to generate a photon count for each zone of the plurality of zones, identifying a focal sector of the field of view and analyzing each zone to select a final focal object from a first prospective focal object and a second prospective focal object.
    Type: Grant
    Filed: September 20, 2023
    Date of Patent: November 12, 2024
    Assignees: STMicroelectronics France, STMicroelectronics, Inc., STMicroelectronics (Research & Development) Limited
    Inventors: Darin K. Winterton, Donald Baxter, Andrew Hodgson, Gordon Lunn, Olivier Pothier, Kalyan-Kumar Vadlamudi-Reddy
  • Patent number: 12138703
    Abstract: The present invention relates to inserts for hard facing substrates, and a method for hard facing substrates. An insert according to an embodiment of the present invention may comprise a body of ultra-hard material having a welding node located on a first surface thereof and at least one wire electrically connecting the first surface to a second, opposite, surface. In use, the inserts may be temporarily connected to a substrate by applying a resistance welding electrode to the welding node, thereby causing the wires on the second surface to melt and weld the insert to the substrate. A subsequent brazing step may firmly attach the inserts to the substrate.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: November 12, 2024
    Assignee: Cutting & Wear Resistant Developments Limited
    Inventors: Mark Russell, Andy Ollerenshaw, Sureshkumar Venkatachalam
  • Publication number: 20240369568
    Abstract: Disclosed herein are stable isotope labeling (SIL) peptide mapping methods for accurate and sensitive conjugation site quantitation. Also disclosed herein are compositions comprising antibody drug conjugates (ADCs) that target BCMA.
    Type: Application
    Filed: August 2, 2022
    Publication date: November 7, 2024
    Applicant: GlaxoSmithKline Intellectual Property Development Limited
    Inventors: Tyler Keith DAVIS, Hillary Amber SCHUESSLER
  • Patent number: 12122828
    Abstract: Provided herein are interleukin 7 (IL-7) binding proteins, pharmaceutical compositions and their use in the treatment or prevention of a disease or condition.
    Type: Grant
    Filed: September 5, 2023
    Date of Patent: October 22, 2024
    Assignee: GlaxoSmithKline Intellectual Property Development Limited
    Inventors: Gerben Bouma, Edward Thomas Coulstock, David Dixon, Stephanie Hopley, Alan Peter Lewis, Jessica Lynn Neisen
  • Patent number: 12091872
    Abstract: Hybrid buildings, hybrid building systems and methods of constructing hybrid buildings are disclosed. First and second building sections forming part of such buildings are also disclosed. One such hybrid residential building (1600) comprises a first building section (1610) and a second building section (1620). The first building section is an on-site construction at a final location for the building and comprises a lower storey (1611) defining an internal volume (1613) that provides a lower living space (1615) within the building, and an upper storey (1617) defining an internal volume (1619) that provides an upper living space (1621) within the building. The second building section defines an internal volume (1623) and is transportable to the final location in a substantially assembled form. The first and second building sections are connected at the final location to form the building.
    Type: Grant
    Filed: March 2, 2023
    Date of Patent: September 17, 2024
    Assignee: Sano Development Limited
    Inventors: David Lee Jones, Edward Ross Shenton, Anthony Robert Cherry
  • Patent number: 12074242
    Abstract: Disclosed herein is an array of pixels. Each pixel includes a single photon avalanche diode (SPAD) and a transistor circuit. The transistor circuit includes a clamp transistor configured to clamp an anode voltage of the SPAD to be no more than a threshold clamped anode voltage, and a quenching element in series with the clamp transistor and configured to quench the anode voltage of the SPAD when the SPAD is struck by an incoming photon. Readout circuitry is coupled to receive the clamped anode voltage from the transistor circuit and to generate a pixel output therefrom, the threshold clamped anode voltage being below a maximum voltage rating of transistors forming the readout circuitry.
    Type: Grant
    Filed: May 2, 2022
    Date of Patent: August 27, 2024
    Assignee: STMicroelectronics (Research & Development) Limited
    Inventors: Mohammed Al-Rawhani, Neale Dutton, John Kevin Moore, Bruce Rae, Elisa Lacombe
  • Patent number: 12066539
    Abstract: A method implemented by a first time of flight (ToF) sensor includes generating, by the first ToF sensor, a first depth map in accordance with measurements of reflections of an optical signal emitted by the first ToF sensor; communicating, by the first sensor with a second ToF sensor, the first depth map and a second depth map, the second depth map generated by the second ToF sensor; and determining, by the first ToF sensor, a relative location of the first ToF sensor relative to the second ToF sensor in accordance with the first depth map and the second depth map.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: August 20, 2024
    Assignee: STMicroelectronics (Research & Development) Limited
    Inventors: Brent Edward Hearn, Marek Jan Munko
  • Patent number: 12066678
    Abstract: An electronic device includes a carrier substrate having a front face. An electronic chip is mounted on the front face of the carrier substrate and includes an optical component. An encapsulation cover is mounted on top of the front face of the carrier substrate and bounds a chamber within which the chip is situated. A front opening extends through the cover and is situated in front of the optical component. An optical element, designed to allow light to pass, is mounted within the chamber at a position which covers the front opening of the encapsulation cover. The optical element includes a central region designed to deviate the light and having an optical axis aligned with the front opening and the optical component. A positioning pattern is provided on the optical element to assist with mounting the optical element to the cover and mounting the cover to the carrier substrate.
    Type: Grant
    Filed: February 16, 2023
    Date of Patent: August 20, 2024
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Research & Development) Limited
    Inventors: Nicolas Mastromauro, Roy Duffy, Karine Saxod
  • Patent number: 12063040
    Abstract: A system-on-a-chip (SOC) within a package includes a reference generator, a matching circuit, a programmable current generator, a PWM controller, an overvoltage/undervoltage detector receiving a high voltage from a third output pad, a multiplexer passing an input signal to a second output pad, and a SPAD receiving the high voltage. Switching circuitry includes a first switch between the reference generator and an input of the programmable current generator, a second switch between the input of the current generator and the output of the matching circuit, a third switch between the reference generator and an input of the matching circuit, a fourth switch between an output of the current generator and a tap of a ladder within the overvoltage/undervoltage detector, a fifth switch between an output of the current generator and the first output pad, and a sixth switch between the output of the PWM controller and the first output pad.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: August 13, 2024
    Assignee: STMicroelectronics (Research & Development) Limited
    Inventors: Neale Dutton, Steven Collins
  • Patent number: 12055435
    Abstract: A sensing pixel includes a single photon avalanche diode (SPAD) coupled between a first node and a second node, with a clamp diode being coupled between a turn-off voltage node and the second node. A turn-off circuit includes a sense circuit configured to generate a feedback voltage based upon a voltage at the turn-off voltage node, a transistor having a first conduction terminal coupled to the turn-off voltage node, a second conduction terminal coupled to ground, and a control terminal, and an amplifier having a first input coupled to a reference voltage, a second input coupled to receive the feedback voltage, and an output coupled to the control terminal of the transistor. A readout circuit is coupled to the SPAD by a decoupling capacitor.
    Type: Grant
    Filed: November 15, 2022
    Date of Patent: August 6, 2024
    Assignee: STMicroelectronics (Research & Development) Limited
    Inventor: John Kevin Moore
  • Patent number: 12057461
    Abstract: An electronic device includes a stack of a first level having a SPAD, a second level having a quench circuit for said SPAD, and a third level having a circuit for processing data generated by said SPAD. A method for making the device includes: a) forming of the first level; b) bonding, on the first level, by molecular bonding, of a stack of layers including a semiconductor layer; and c) forming the quench circuit of the second level in the semiconductor layer.
    Type: Grant
    Filed: July 24, 2023
    Date of Patent: August 6, 2024
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Research & Development) Limited
    Inventors: Francois Guyader, Sara Pellegrini, Bruce Rae
  • Patent number: 12032074
    Abstract: A tracking device includes a location module arranged to determine a location of the tracking device; a communication gateway arranged to communicate the location of the tracking device to a receiver station; and a housing arranged to house the location module and the communication gateway, wherein the housing is further arranged to engage with an access mechanism such that when the access mechanism is actuated, the housing is manipulated.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: July 9, 2024
    Assignee: First Dragon Development Limited
    Inventors: Kenneth Hitchens, William Harold Pike, II, Christane Machado
  • Publication number: 20240221358
    Abstract: A system may determine, for each frame of a plurality of frames of image data associated with a vehicle, a probability that each frame of the plurality of frames that includes an image of a stop sign is relevant to the vehicle. The system may determine a longest sequence of consecutive frames of the plurality of frames for which the probability satisfies a probability threshold. The system may determine a maximum probability associated with a frame included in the longest sequence of consecutive frames. The system may determine a time window based on a time associated with the frame associated with the maximum probability. The system may determine location data and sensor data for the vehicle based on the time window. The system may determine an occurrence of a stop sign violation based on the location data and the sensor data.
    Type: Application
    Filed: January 12, 2024
    Publication date: July 4, 2024
    Applicant: Verizon Connect Development Limited
    Inventors: Luca BRAVI, Luca KUBIN, Leonardo TACCARI, Francesco SAMBO, Matteo SIMONCINI, Douglas COIMBRA DE ANDRADE, Stefano CAPRASECCA
  • Patent number: D1053891
    Type: Grant
    Filed: September 8, 2022
    Date of Patent: December 10, 2024
    Assignee: GlaxoSmithKline Intellectual Property Development Limited
    Inventors: Kaushal Kishore, Mala Kiran Talekar