Abstract: Described is a rectification circuit to generate a direct current at an output of the rectification circuit subject to an alternating voltage at an input of the rectification circuit. The rectification circuit comprises: coupling means at the input to receive the alternating voltage from a galvanically decoupled electronic subsystem; a first switch arranged between the coupling means and the output to block current in a first direction and to conduct current in a second direction, wherein a resistance of the first switch is adjustable; a first modulation unit to receive encoded information; mapping the encoded information to a first modulation state, wherein each modulation state specifies a resistance value and/or a temporal evolution of the resistance value; adjusting the resistance of the first switch, thereby modulating the current conducted by the first switch according to the first modulation state.

Abstract: An apparatus and method for a boost power converter with improved electrical overstress (EOS) tolerance is disclosed. A boost power converter provides a providing a pulse width modulation (PWM) boost power converter with an electrical overstress (EOS) boost over-voltage comparator/switch network comprises a boost power converter, a boost overvoltage comparator, a boost overvoltage comparator feedback network, and a boost overvoltage switch. The methodology for the boost converter with improved electrical overstress (EOS) tolerance defines an absolute maximum voltage condition, provides a voltage limit below the defined absolute maximum voltage condition, and initiates turn-on of the boost overvoltage switch according to the voltage limit.

Abstract: A dual mode low dropout voltage regulator has a low dropout regulation mode and a bypass mode and provides a smooth transition between mode transitions taking place under load. When an accessory requires a larger voltage level, a bypass signal commands the dual mode low dropout voltage regulator to go into bypass mode and transfer voltage level of the unregulated input voltage source to the output of the dual mode low dropout voltage regulator. The dual mode low dropout voltage regulator provides a smooth transition to the bypass to prevent the output of the dual mode low dropout voltage regulator from decreasing or having a “brown out” until a pass transistor is forced to turn on fully to provide the voltage level of the unregulated input voltage source to fully bypass the low dropout regulating mode of operation.

Abstract: The present document relates to the programming of programmable memory devices, e.g. one-time programmable (OTP) memory device. In particular, the present document relates to efficient methods and systems for generating the supply voltage for programming a programmable memory device. A controller configured to control the programming of a data word into a programmable memory device is described. The controller is configured to set one or more digital control signals for programming the data word into the programmable memory device. Furthermore, the controller is configured to, subsequent to setting the one or more digital control signals, increasing a device supply voltage for the programmable memory device from a default operation level to a programming level.

Abstract: The present document relates to the control of high side switches, e.g. the high side switches of half bridges. In particular, the present document relates to an efficient control circuit for controlling a plurality of high side switches. A control circuit for controlling a plurality of parallel high side switches of a respective plurality of parallel bridges is described. The control circuit comprises a charge provisioning unit configured to provide an electrical charge. Furthermore, the control circuit comprises a plurality of sets of high control switches for the plurality of high side switches, respectively; wherein each set of high control switches is configured to arrange the charge provisioning unit in parallel to a gate-source capacitance of the respective high side switch.

Abstract: A pass device configured from a common gate transistor, wherein an input voltage is applied to the source and an output at the drain is applied to a load. The input resistance of the pass device increases as the input voltage is reduced and limits the useful range of the input voltage. Increasing the gate to source voltage (Vgs) by applying a negative voltage to the gate reduces the input resistance and increases the range of operation of the pass device.

Abstract: A pass device configured from a common gate transistor, wherein an input voltage is applied to the source and an output at the drain is applied to a load. The input resistance of the pass device increases as the input voltage is reduced and limits the useful range of the input voltage. Increasing the gate to source voltage (Vgs) by applying a negative voltage to the gate reduces the input resistance and increases the range of operation of the pass device.

Abstract: This invention provides a switching converter having a plurality N of outputs providing N output signals and at least one inductor, comprising a first controlling device for controlling the total energy flowing over the inductor to the N outputs dependent on a first control signal, at least a second controlling device for distributing the total energy between the N outputs by means of at least a second control signal, wherein the first controlling device is coupled to all N outputs for receiving a number M of the respective feedback output signals of the N outputs, M?N, wherein the first controlling device comprises first means for weighting the M feedback output signals and second means for providing the first control signal dependent on the weighted M feedback output signals.

Abstract: A low dropout (LDO) regulator with a limited startup inrush current is disclosed. The LDO includes a power source, error amplifier, pass transistor, feedback network, and a current limit control whose input is electrically connected to the pass transistor and the electrical output of the error amplifier and whose output limits current during startup. The LDO can include a current control limit comparator including a power source, and output of the pass transistor. The LDO can also include a bypass mode current control limit comparator having a first input voltage of the error amplifier, and a second input voltage from the error amplifier.

Abstract: Methods and circuits for CMOS relaxation oscillators are disclosed. A single capacitive element, a single current source and a switching network are utilized. A switching network of the oscillator allows both nodes of the capacitive element to rise and fall between a positive and a negative voltage with respect to ground supply, without causing leakage to substrate or risk of latch-up, i.e. the inadvertent creation of a low-impedance path. The oscillator requires minimum silicon area, has an improved duty cycle, is particular useful for implementing lower frequency clocks and is enabled for smaller technology nodes, lower than 250 nm, due to lower supply voltage.

Abstract: An anode driver chip and a cathode driver chip attached to an OLED device by means of anisotropic glue. The fine structure of the attachment means requires inspection to determine any resulting open and short conditions. The anode driver circuits comprise an output current detection that allows open circuit testing of the contact between the OLED device and the anode driver chip. The cathode driver circuits comprise a voltage detection circuit that allows both open and short circuit detection between cathode driver pads.

Abstract: A digital active noise cancellation circuit device (330) includes an oversampled, sigma-delta, A/D converter (204), a digital decimation filter (208), a digital intermediate filter (308), a digital interpolation filter (232), and a sigma-delta, D/A converter (252).

Abstract: The present document relates to providing power for driving SSL devices. A power converter converts a varying input voltage to supply an output voltage to a SSL device in series with a current source. The power converter comprises one or more capacitors; a plurality of switches to couple the capacitors in a plurality of configurations. A control unit operates the power converter in a plurality of operational modes providing a corresponding plurality of different conversion ratios between the input/output voltages. The operational modes comprise a first phase and a second phase, during which the capacitors are differently arranged. The control unit controls the switches to alternate between the phases at a commutation cycle rate. The control unit sets the operational mode based on the varying input voltage.

Abstract: The present document relates to solid state lighting (SSL) devices. A driver circuit for phase-cut dimmable SSL based lighting assemblies is described. A control circuit for a power converter is provided. The power converter is configured to convert an input power derived from a mains power supply into a drive power for a light source. The control circuit comprises a dimmer mode detection unit to determine a first dimmer mode. The first dimmer mode indicates if the input power has been derived from the mains power supply using a dimmer. The control circuit comprises a state processor configured to determine a first operation mode of the power converter. The pre-determined first state information is dependent on the first dimmer mode. The control circuit comprises a first control unit configured to generate a first control signal for operating the power converter in accordance to the first operation mode.

Abstract: Circuits and methods for current limited DC-to-DC converters having multiple power sources have been disclosed. One of multiple power sources is activated by a multiplexer. A current sensing unit, deployed close to the multiplexer, detects if an input current to the DC-to-DC converter has reached a current limit. In case the current limit is reached a signal is sent to the DC-to-DC converter to reduce the current drawn the DC-to-DC converter.

Abstract: The present document relates to multi-stage amplifiers, such as linear regulators or linear voltage regulators (e.g. low-dropout regulators) configured to provide a constant output voltage subject to load transients. A multi-stage amplifier is described. The multi-stage amplifier comprises a first amplification stage configured to provide a stage output voltage at a stage output node. Furthermore, the amplifier comprises an intermediate amplification stage comprising an amplifier current source configured to provide an amplifier current and an amplifier transistor arranged in series with the amplifier current source. A gate of the amplifier transistor is coupled to the stage output node of the first amplification stage. The intermediate amplification stage is configured to provide an amplified or attenuated stage output voltage at a midpoint between the amplifier current source and the amplifier transistor.

Abstract: The present document relates to multi-stage amplifiers, such as linear regulators or linear voltage regulators (e.g. low-dropout regulators) configured to provide a constant output voltage subject to load transients. A multi-stage amplifier is described, having a differential amplification stage which comprises a differential transistor pair. The differential amplification stage is configured to provide a stage output voltage at a stage output node of the differential transistor pair, based on a first input voltage at a first stage input node and a second input voltage at a second stage input node. The differential transistor pair also comprises a reference node. The differential amplification stage further comprises an active load comprising a first diode transistor coupled to the reference node and a first mirror transistor coupled to the stage output node.

Abstract: Circuits and methods providing a electronic power supply applicable to any dual supply rail systems, which require a smooth and uninterrupted output supply and a replica power path and autonomous mode of operation from the system power supply are disclosed. In a preferred embodiment of the invention the power supply is applied to a real time clock. An Innovative Replica Power Path concept and circuit implementation ensures the smooth and uninterrupted transfer of power from one input source to the other. The circuit features a Latched Supply Comparator that guarantees the commutation to the Replica Power Path only happens after the voltage is settled. Zero power consumption from the back-up energy source is achieved in the presence of an alternative higher voltage source. The generated RTC supply voltage does not suffer from abrupt changes when the voltage level of the main system power source (battery or charger) is connected or disconnected.

Abstract: Circuits and methods prevent ringing of white LED drivers by adding a high voltage coil switch (CS) circuit, a high voltage edge detector circuit, and a boot strap circuit. The coil switch (CS) circuit to short the coil of a boost converter, when the current in it reaches zero during DCM, comprises a series of 2 identical HV enhancement NMOS with bulk switch system. An Edge Detector circuit senses the fast falling edge of an LX node. A Boost Strap circuit lifts the gate of coil switch circuit above the battery voltage level and turns on the coil switch. A Boost Strap (BS) system lifts the gate of CS above the VBAT level and turns on CS, wherein minimum current is required to minimize impact on efficiency.

Abstract: The present document relates to the measurement of the current through a transistor. In particular, the present document relates to a circuit arrangement which allows an accurate measurement of the current through a power transistor. A circuit arrangement is described. The circuit arrangement is configured to provide an indication of a current flowing through a pass switch, when the pass switch is arranged in parallel to the circuit arrangement. The circuit arrangement comprises a matching unit which comprises a switch bank comprising a plurality of parallel reference switches; a resistor bank comprising a plurality of serial reference resistors; and a reference current source configured to provide a reference current flowing through the switch bank and the resistor bank. The resistor bank and the switch bank are arranged in series.