Abstract: The present document relates to voltage regulators (101). In particular, the present document relates to the testing of voltage regulators subject to load transients. A test device (110) configured to generate a load current to be drawn at an output of a voltage regulator (101) is described. The test device (110) comprises a load connector (116) for coupling the test device (110) to the output of the voltage regulator (101); a transistor (113) configured to modulate the current through the load connector (116) subject to a control signal (123); wherein the current through the load connector (116) corresponds to the load current; a current sense resistor (112) arranged in series with the transistor (113) and configured to provide a feedback voltage (121) which is substantially proportional to the load current; and an operational amplifier (111) configured to generate the control signal (123) based on the feedback voltage (121) and based on a target voltage (122).

Abstract: Circuits and methods to achieve a new fully differential amplifier topology in class AB mode are disclosed. In a preferred embodiment of the disclosure the differential amplifier is diving dynamic speakers. An differential intermediate stage combines four different feedbacks, all sharing four high impedance nodes: main loop regulation feedback, common mode regulation feedback, and output stage quiescent current regulation for both differential output stage branches.

Abstract: The present document relates to a method and system for determining the voltage level of an input signal compared to a reference voltage, providing a plurality of level indications regarding an input voltage with respect to a reference voltage. The multi-level comparator comprises an input stage converting the input voltage into a first current and converting the reference voltage into a second current; and a plurality of comparator stages, each comprising a first current amplification unit amplifying the first current with a first gain, a second current amplification unit amplifying the second current with a second gain, and an output port providing an indication whether the first comparator current is smaller or larger than the second comparator current; wherein respective ratios of the first gain and the second gain of the plurality of comparator stages are different.

Abstract: Systems and methods for providing a rapid switchable high voltage power transistor driver with a constant gate-source control voltage have been disclosed. A low voltage control stage keeps the gate-source voltage constant in spite of temperature and process variations. A high voltage supply voltage can vary between about 5.5 Volts and about 40 Volts. The circuit allows a high switching frequency of e.g. 1 MHz and minimizes static power dissipation.

Abstract: In order to control of dimming of solid state lighting devices (SSL) a driver circuit drives the SSL subject to an input voltage using a phase-cut dimmer. The driver circuit comprises a transistor operable in two modes, either alternating between on/off states or continuously controlling a current through the transistor. A power converter network provides a switched-mode power converter in conjunction with the transistor when operated in the first mode generating a drive voltage for the SSL. The control unit controls the transistor to selectively operate in one of the two modes; to control the transistor to determine that the input voltage exceeds an input voltage threshold; and to control a drive current through the SSL based on a measurement of a phase-cut angle thereby controlling an illumination level of the SSL device.

Abstract: The present document relates to a reduction of heat generated in driver circuits comprising voltage regulators. A circuit arrangement comprises a driver circuit configured to generate a control signal for driving a power switch. The driver circuit comprises a voltage regulator configured to generate a second voltage from a supply voltage, a drive unit configured to generate the control signal based on the supply voltage and configured to provide the control signal to a control interface of the driver circuit, and a logic component operating at the second voltage and drawing a second current, and configured to control the drive unit. Furthermore, the circuit arrangement comprises bypass circuitry coupled at an input to the control interface and configured to provide at an output at least part of the second current to the logic component.

Abstract: Circuits and methods to achieve a most efficient driver for white LEDs are disclosed. Switching Losses associated with the switching activity of a boost converter and mainly depending on clock frequency and total capacitance at the switching nodes and conduction losses associated with the current flowing in the boost converter and mainly depending on the series resistance of the elements in the regulation loop are minimized by using a size programmable NFET power switch with constant current limit, a very low voltage and accurate programmable current source, a programmable reference voltage for the error amplifier, and a PWM generator with programmable clock frequency. A limited number of configuration windows corresponding to a set of programmable values (OTP registers) for specific ranges of the current fed to the WLEDs.

Abstract: A power management IC (PMIC) and methods thereof have been achieved wherein the PMIC invented supports multiple applications while having a high degree of flexibility and allowing a small built and a low power consumption. An embedded script engine on an internal communication bus of the PMIC replaces hard-wired sequencers and control interfaces or using processors as utilized in prior art. The script engine reads instructions from a non-volatile memory as e.g. a one-time programmable (OTP) memory. Furthermore a RAM can be provided to store executable instructions loaded from a host. Moreover a FIFO process is provided if instructions or TAGs are received while a previous script is being exercised. Any type of power supplies, output GPIO or other function could be controlled also by the Script Engine. The invention is also applicable to any other kind of power management circuits.

Abstract: An amplifier circuit and a method of amplification using automatic gain control (AGC) are disclosed. A method for reducing distortions incurred by an audio signal when being rendered by an electronic device is described. The method comprises receiving an input signal; determining signal strength; determining a frequency-dependent AGC filter; wherein the frequency-dependent AGC filter is adapted to selectively attenuate the input signal within a number N of predetermined frequency ranges, according to corresponding N degrees of attenuation; wherein N predetermined frequency ranges depend upon a rendering characteristic of the electronic device; and wherein the N-degrees of attenuation depend upon the signal strength; and attenuating the input signal using the frequency-dependent AGC filter to obtain an output signal for rendering by the electronic device.

Abstract: A circuit for a flat panel display, capable of displaying images, is provided. The circuit includes an image storage and processing block for the images to be displayed, a display and timing controller block controlling the display operation, an image pixel matrix containing a multitude of rows and columns arranged pixel elements. The circuit also includes one or more controlled row driver blocks, one or more controlled column driver blocks, and a pixel display operation for displaying pixel elements employing an advanced multi line addressing operation applied to a row and/or column drive activated pixel element display operation.

Abstract: This invention discloses circuit and methods of a NAND-based 2T-string NOR flash cell structure as a building block for a fast random-read NOR flash memory. The key concept of this new set of bias conditions in cell array improves over the critical concern of punch-through issue when cell is migrating to the more advanced technology node of next generation. The invention adopts a novel preferable symmetrical 2T-string NOR flash cell. Each NAND or NAND like cell of this 2T-string NOR cell is to store 2 bits and is preferable to be made of N-channel device. The cell is preferable to use Fowler-Nordheim Tunneling scheme for both erase and program operations- The invention is to provide a novel 2T-string NOR flash cell structure made of N-channel device offering most flexible erase sizes in unit of byte, page, sector, block and chip with the least program and erase disturbances.

Abstract: A self-biased reference circuit device (100) includes a first cascode current mirror (116), a second cascode current mirror (118), and a startup circuit (108). The first cascode current mirror (116) is capable to generate a first bias voltage (136) and a second bias voltage (140) in response to a first current and to generate a second current in response to the first and second bias voltages. The second cascode current mirror (118) is capable to generate a third bias voltage (164) in response to the second current, to generate a fourth bias voltage (168) in response to a third current, and to generate the first current in response to the third and fourth bias voltages. The startup circuit includes a first switch (188) and a second switch (196). The first switch (188) is capable to connect the first bias voltage (136) and fourth bias voltage (168) during startup.

Abstract: The present document relates to chip sockets which for testing integrated circuit chips. A chip socket carries an integrated circuit chip comprising a plate for mounting onto a front side of a PCB, a plurality of electrical PCB connectors in a first area on a backside of the plate, wherein the plurality of electrical PCB connectors is adapted for electrically connecting the chip socket to a corresponding plurality of connectors on the PCB and a corresponding plurality of chip connectors on a front side of the plate, wherein the plurality of chip connectors is electrically connected to the plurality of electrical PCB connectors respectively; wherein the plurality of chip connectors connect the chip socket to a corresponding plurality of connectors of the integrated circuit chip, wherein the plate comprises a recess at its backside.

Abstract: Systems and methods are disclosed for a display driver having an internal non-volatile memory in order to save memory storage and computation effort of a host processor. In a preferred embodiment of the invention the display driver is applied for an electronic paper display. Contained within the display driver are user-definable display graphics bitmaps, multiple stored bitmaps used to assemble complex display images, and multiple phase tables, each table of arbitrary length. The invention removes the requirement for a host processor to store display images and/or display image decodes of numerical data and simplifies the process required to construct a display image from stored bitmaps. Furthermore the invention provides pre-programmed multiple phase tables (phase/delay waveform definitions), allowing a simple mechanism to alter the waveform generation, required for example to accommodate temperature variations, blanking the display before updating an image, etc.

Abstract: An electrolyte-based battery cell, having a positive electrode active material layer formed adjacent to a positive electrode collector, a negative electrode active material layer formed adjacent to a negative electrode collector, a separator which has surfaces facing respective surfaces of said active material layers, an electrolyte kept within the separator, the active material layers and there between, and a conductivity measuring means for measuring an electric conductivity of the electrolyte. Also disclosed are a system, and method, for determining the state of charge of an electrolyte-based battery.

Abstract: The present document discloses a driver circuit for the high side switch of a half bridge at ultra-high voltage. The half bridge comprises the high side switch coupled to an input voltage Vin and to a midpoint of a low side switch. The driver circuit comprises a control signal generation unit generating a stream of control pulses and a control logic generating a gate voltage for the high side switch using a supply voltage Vcc based on the control pulses, a supply voltage capacitor generating the supply voltage Vcc, and a decoupling capacitor coupled on a first side to the control signal generation unit and on a second side to the control logic, to the midpoint of the half bridge via a first charging switch, and to the supply voltage capacitor via a second charging switch.

Abstract: A method and system for limiting the slew rate of the output voltage of one or more high side (HS) NMOS power switches is disclosed. A circuit arrangement configured to control a first NMOS switch is described. The arrangement comprises voltage provisioning means configured to supply a gate voltage to a gate terminal of the first NMOS switch; current provisioning means configured to provide a current; a first control stage configured to provide and/or remove a connection between the gate terminal of the first NMOS switch and the voltage provisioning means, thereby switching the first NMOS switch to an on-state and/or an off-state, respectively; and a first feedback control link between an output terminal of the first NMOS switch and the current provisioning means configured to control the slew-rate of a voltage at the first output terminal.

Abstract: Circuits and methods for dynamic adjustment of the current limit of a power management unit to avoid unwanted automatic interruption of the power flow have been disclosed. The invention can be applied to switched and linear DC-to-DC converters. The power management unit is automatically adjusted to the output resistance of a power source (including interconnect resistance). The invention maximizes the time and hence the power transferred from a power management unit to the system (including the battery, in case of battery operated systems). The input current is reduced, thus increasing the input voltage in case of a high voltage drop across the internal resistance including interconnections between power source and power management unit.

Abstract: The present disclosure provides circuitry and a method for digital clock generation including the generation of integer and non-integer sub clocks. The proposed method provides simplified constant signal propagation and low skew in the divided clock path independent of division factor. Also provided is a simplified mechanism for generating low power clock patterns divided down by factors which are non-integer, phase-shifted, repeated pulse trains, dynamically changing and glitch-free.

Abstract: Circuits and methods to prevent ringing of white LED drivers by adding a high voltage coil switch circuit, a high voltage edge detector circuit, and a boot strap circuit are disclosed. The coil switch circuit to short the coil of a boost converter when the current in it reaches zero during DCM, comprises a series of 2 identical HV enhancement NMOS with bulk switch system. The Edge Detector circuit senses the fast falling edge of the LX node. The Boost Strap circuit lifts the gate of coil switch circuit above the battery voltage level and turns on the coil switch.