Abstract: It is an object of one or more embodiments of the present disclosure to provide a power stage overdrive circuit, at low supply voltages, that can be enabled/disabled on the fly. The power stage overdrive circuit increases the overdrive of a power switch to allow for simple power stage architecture with high voltage PMOS and NMOS devices. The power stage overdrive circuit comprises a driver, configured to drive the power switch having a control terminal, for example a gate terminal, and a boost circuit, further comprising a boost capacitor having a first terminal coupled to a power supply, for example a battery, and a second terminal coupled to the control terminal, configured to provide an overdrive voltage to the control terminal to turn the power switch on.

Abstract: A switching power converter is configured to control switching noise by implementing a plurality of pulse width modulation modes of operation. The peak current in each pulse width modulation mode of operation is controlled so that an output power for the switching power converter is continuous with regard to transitions between the pulse width modulation modes.

Abstract: An inductor arrangement has a first inductor structure having one or more inductors at least partially on a first layer and a second inductor structure having one or more inductors at least partially on a second layer. The inductors are arranged such that currents induced by an external magnetic field are substantially cancelled in at least one of the first inductor structure and the second inductor structure. The, or each, inductor of the second inductor structure overlaps, at least partially, the, or each, inductor of the first inductor structure. An oscillator circuit having an inductor arrangement is also presented.

Abstract: A sigma-delta modulator and method for converting an input voltage such as an analog signal into a digital signal is presented. The modulator may be used as an analog-to-digital converter (ADC). The modulator has a plurality of bias transistors with at least one p-type transistor and at least one n-type transistor. The modulator receives a bias voltage, wherein each bias transistor receives the same bias voltage. This sigma-delta modulator results in reduced power consumption.

Abstract: An auto-calibrated current sensing comparator is provided. A secondary dynamic comparator shares the same inputs and acts to adjust a calibration control of the current sensing comparator. The calibration control may be in the form of adjusting the offset of the current sensing comparator or adjusting a propagation delay that is added to its output.

Abstract: A switching power converter is disclosed that communicates a thermal alarm to a mobile device over a data channel in a data cable for charging the mobile device.

Abstract: A multi-level buck converter is provided with multiple control loops to regulate the output voltage in the presence of over-current conditions and in the vicinity of a 50% duty cycle.

Abstract: A linear regulator with a pass device having a first terminal, a second terminal and a drive terminal is presented. The first terminal of the pass device is coupled with the supply voltage of the linear regulator. The second terminal of the pass device is coupled with the output of the linear regulator. A driver stage is coupled with the supply voltage of the linear regulator, and the drive terminal of the pass device drives the pass device with a driving voltage. A compensating circuit compensates for a change in a voltage difference between the drive terminal of the pass device and the supply voltage of the linear regulator.

Abstract: A direct charging method is provided that alerts a mobile device when a switching power converter is operating in a constant-current mode to alert the mobile device of an output current without the use of a secondary-side current sense resistor.

Abstract: There is provided a signal generator and associated method for generating a source signal. The signal generator includes a frequency generator for providing an oscillating signal, a phase comparator, a first phase modulator, a second phase modulator and a phase shifter. The phase comparator is adapted to compare a phase signal with a feedback signal and to generate an error signal to control the phase of the oscillating signal. The first and second phase modulators are adapted to provide a first phase control word and a second phase control word respectively. The phase shifter is adapted to modulate the oscillating signal based on the second phase control word to generate the source signal. The source signal comprises the feedback signal.

Abstract: Systems, methods, and apparatus for a circuit with power factor correction (PFC) are disclosed. In one or more embodiments, the disclosed method comprises providing, by a single-stage power converter, a delay in phase between a peak current command and a rectified input voltage such that a phase of a transformer current intentionally lags behind a phase of the rectified input voltage to maintain a power factor (PF) level and a total harmonic distortion (THD) level for the single-stage power converter. In one or more analog embodiments, a resistor and a capacitor are implemented into a conventional single-stage power converter to provide the delay in phase between the peak current command and the rectified input voltage. In one or more digital embodiments, a controller within a conventional single-stage power converter exclusively provides the delay in phase between the peak current command and the rectified input voltage.

Abstract: A switching power converter is provided that adaptively changes the on-time period for an auxiliary switch transistor to locate a boundary between sufficient and insufficient energy.

Abstract: Power converters, charge pumps and methods which are capable of regulating output voltage are presented. A power converter has a capacitive element, a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor is coupled between an input terminal and a first terminal of the capacitve element. The second transistor is coupled between the first terminal of the capacitve element and an output terminal. The third transistor is coupled between the output terminal and a second terminal of the capacitive element. The fourth transistor is coupled between the second terminal of the capacitive element and a reference potential. The power converter has a control circuit to control, during a first time interval of a voltage regulation mode, one of the four transistors such that the one of the four transistors is operated as a controllable power source for regulating an output voltage.

Abstract: A system and method for controlling a light output from a LED-based lighting solution is provided that may receive phase-cut AC signals and/or external digital control signals. The invention is capable of receiving both a phase-cut AC signal and an external digital control signal simultaneously and providing a desired light output from a LED-based lighting solution. The system generally includes a power source electronically connected to one or more dimmers and an AC power output of the dimmer connected to a solid state lighting device such as an LED. The system is capable of receiving signals from a wired and/or wireless external digital control device to additionally control the desired light output from a LED-based lighting solution.

Abstract: Control circuitry for controlling the duty cycle of a magnetizing switch of a power converter containing a demagnetizing switch is described. The magnetizing switch and the demagnetizing switch are switched on within a sequence of commutation cycles in a mutually exclusive manner. The control circuitry is configured, within a commutation cycle from the sequence of commutation cycles, to determine a sensed current signal indicative of a current through the magnetizing switch. The control circuitry determines a ramp signal by adding a slope compensation signal to the sensed current signal. The control circuitry determines a threshold signal and determines a duty cycle for the magnetizing switch for the commutation cycle by comparing the ramp signal with the threshold signal. The threshold signal and/or the slope compensation signal depend on the duty cycle for the magnetizing switch of a preceding commutation cycle from the sequence of commutation cycles.

Abstract: Power converters and method with reverse charge capability are presented. A power converter operates either in a buck mode for transferring electrical power from a first terminal of the power converter to a second terminal of the power converter, or in a boost mode for transferring electrical power from the second terminal of the power converter to the first terminal of the power converter. The power converter has several switching elements, a flying capacitor, an inductor, and a control unit. The switching elements couple the first terminal of the power converter and the flying capacitor, couple the first terminal of the flying capacitor and a first terminal of the inductor, couple the first terminal of the inductor and a second terminal of the flying capacitor and couple the second terminal of the flying capacitor and a reference potential. The control unit controls the switching elements.

Abstract: A DC-DC current-control mode switching converter is disclosed, with peak-mode control circuitry, configured to compare a coil current to a variable current limit, to turn off a high side device when the coil current exceeds the variable current limit. The DC-DC switching converter includes a compensation ramp generator, configured to provide a compensation ramp signal, and an offset circuit, configured to provide an offset current. The DC-DC switching converter further includes an amplifier, configured to generate a control current proportional to the difference between an output voltage and a target voltage, and an adder, to combine the control current, the compensation ramp signal, and the offset current. A DC-DC current-control mode switching converter, with valley-mode control circuitry, configured to compare a coil current to a variable current limit, to turn off a low side device when the coil current falls below the variable current limit, is also disclosed.

Abstract: A multi-phase switching power converter is disclosed in which the duty cycle of active phases following a phase shedding transition is temporarily adjusted to increase the operating speed of the multi-phase switching power converter.

Abstract: A switching mode power converter circuit is disclosed, comprising a first high-side switch and a first low-side switch coupled in series between an input voltage level and a reference voltage level, a second high-side switch and a second low-side switch coupled in series between the input voltage level and the reference voltage level, and a control circuit for controlling switching operation of the first and second high-side switches and the first and second low-side switches. The first high-side switch has a larger on-state resistance than the second high-side switch and the first low-side switch has a larger on-state resistance than the second low-side switch. The control circuit is configured to, during an on-state of the first and second low-side switches, control the second low-side switch to switch to the off-state and control the first high-side switch to switch to the on-state, so that the first high-side switch and the first low-side switch are both in the on-state.

Abstract: A DC-DC switching converter, with a low IQ hysteretic-PWM automated hybrid control architecture, switching from a first mode to a second mode, when load current changes, is described. The DC-DC switching converter provides a simple architecture for a Boost converter, with efficiency high over the entire load range, and with a hybrid hysteretic-PWM control providing a way to automatically switch between modes, without the addition of a sensing element or system complexity. The switching converter uses a voltage comparator to detect the output current is below a certain threshold. A comparator on the error voltage detects the average value of the error signal with relation to the sawtooth signal. If the average value of the error signal is below a threshold for longer than a programmable timer, the main loop is turned off and the system goes into burst mode.