Abstract: A voltage regulator is presented. The output node of the voltage regulator is coupled to an output capacitor via a conductive path that exhibits a parasitic inductance. The voltage regulator has an output amplification stage for deriving the output current at the output node from the input voltage at the input node in dependence of a drive voltage at an intermediate node of the voltage regulator. The voltage regulator has an intermediate amplification stage for providing the drive voltage at the intermediate node based on a differential output voltage. A differential amplification stage determines the differential output voltage in dependence of the output voltage and in dependence of a reference voltage. The voltage regulator has a sensing unit to provide a load indication which is indicative of the output current and a variable impedance coupled to the intermediate node, where the variable impedance is dependent on the load indication.

Abstract: A servo block in a Buck, Boost, or switching converter allows a positive offset to be applied to the DAC voltage. In a typical switching converter application, the load will have a positive current, sourced from the switching converter to ground through the load. This will cause the output voltage of the switching converter to fall with the output impedance. The servo block corrects the output voltage by adjusting the DAC voltage upwards. In the case where current is forced back into the switching converter, causing the output voltage to rise, the servo block will have affect. The behavior of the servo block is desirable as it reduces the negative affect the servo block may have on load transients occurring when the switching converter is in over voltage. In particular, the idea of shifting the DAC voltage for several different loops with a single servo block is disclosed.

Abstract: A switching power converter and a method for receiving an input power at an input node and outputting an output power at an output node is presented. The switching power converter has a high-side switching device coupled between the input node and the output node, a low-side switching device coupled between the input node and a predetermined voltage level, and an active snubber circuit for suppressing voltage peaks at the input node. The active snubber circuit has a first capacitor coupled to the output node. The first capacitor is charged during a first dead time after the low-side switching device has been switched OFF and before the high-side switching device is switched ON.

Abstract: A gate drive circuit arranged to receive an input signal and provide an output signal to drive a gate of a transistor is presented. The gate drive circuit comprises a filter circuit arranged to attenuate a frequency band from the input signal when deriving the output signal from the input signal. The filter circuit contains programmable resistive elements, comprising: a first programmable resistive element arranged to adjust a low frequency gain and bandwidth of the gate drive circuit; a second programmable resistive element arranged to adjust a high frequency gain of the gate drive circuit; and a pair of programmable resistive elements arranged to adjust a driving gain of the gate drive circuit. A method of receiving an input signal and deriving an output signal from an input signal is also presented. The step of deriving an output signal comprises attenuating a frequency band from the input signal.

Abstract: A circuit and a method using a pass device that is coupled between a supply voltage level and a load-connectable node of the circuit for providing a load current. A sense device forms a current mirror with the pass device. The sense device has transistor devices that can be switched to an active state, to adjust a mirror ratio of the current mirror. A first feedback loop regulates a voltage drop across the pass device to a predetermined value. A second feedback loop regulates a voltage drop across the sense device to the voltage drop across the pass device. Measurement circuitry sets a mirror ratio of the current mirror based on an indication of a current flowing through the sense device and generates an indication of current flowing through the pass device based on the set mirror ratio and the indication of the current flowing through the sense device.

Abstract: A current sensing circuit is described. The current sensing circuit is for sensing a high side current through a high side switch and/or for sensing a low side current through a low side switch of a half bridge comprising the high side switch and the low side switch, which are arranged in series between a high side potential and a low side potential. The high side switch and the low side switch are in respective on-phases in a mutually exclusive manner. The high side sensing circuit comprises mirroring circuitry to mirror a current from a first node of the high side sensing circuit to an output node of the high side sensing circuit. The current sensing circuit comprises a low side sensing circuit to provide a sensed low side current which is indicative of the low side current during an on-phase of the low side switch.

Abstract: A flyback converter controller is provided with a single terminal through which the flyback converter controller senses for over-voltage faults for an input voltage and also senses for open circuit faults for an auxiliary winding. A first voltage divider provides a divided version of the input voltage to the single terminal. The controller compares a voltage for the single terminal to at least one over-voltage threshold to detect the over-voltage fault for the input voltage.

Abstract: An output voltage calibration circuit and technique is disclosed to increase the accuracy and precision of the constant-voltage mode for a flyback converter.

Abstract: A power converter for converting an input voltage at an input port into an output voltage at an output port of the power converter is described. The power converter comprises an inductor having a first inductor port and a second inductor port, wherein the second inductor port is coupled to the output port. Furthermore, the power converter comprises a flying capacitor having a first capacitor port and a second capacitor port, and a switching cell. In addition, the power converter comprises a control unit to operate the switching cell in a first sequence of operation phases to perform step-up conversion; and in a second sequence of operation phases to perform step-down conversion.

Abstract: A solid state lighting SSL assembly comprises an SSL device, a capacitor, a directional conducting device and a supply switch. The capacitor is coupled in parallel with the SSL device. The directional conducting device is coupled between an output terminal of the capacitor and a supply terminal which provides a supply voltage for the SSL assembly. The directional conducting device is configured to conduct in a direction from the output terminal to the supply terminal and to isolate in the opposite direction. The supply switch is coupled between the output terminal and ground. In addition, a method for operating a solid state lighting SSL assembly is proposed.

Abstract: A method of establishing a low latency connection between a first device and a second device on a wireless network is presented. The method contains the steps of: forming a first wireless connection between the first and second devices; forming at least a second and parallel wireless connection between the first and second devices; and sending data between the first and second devices using at least the first and second connections. For any wireless protocol for data exchange between devices that specifies a minimum interval between data exchange events, the present disclosure enables a lower latency than would otherwise be achievable according to a standard protocol.

Abstract: Methods, structures and computer program products for digital sample rate conversion are presented. An input digital sample with a first frequency is converted to an output sample with a second frequency. A sample rate conversion circuit is provided which provides an enhanced transposed farrow structure that enables an optimised trade-off between noise levels and computational complexity. Each output sample is derived by convolution of a continuous time interpolation kernel with a continuous time step function representing the input sample stream. In a sample rate conversion structure, there is a trade-off between the quality and the computational complexity. The quality is defined as a ratio between the (wanted) signal power and the (unwanted) noise power. The computational complexity may be defined as the average number of arithmetic operations that are required to generate one output sample. A higher computational complexity will generally lead to a higher power consumption and larger footprint.

Abstract: A circuit for operating a transistor device that acts as a switch is presented. The circuit includes the transistor device and a control circuit coupled to a gate of the transistor device. The control circuit is adapted to selectively apply at least a first voltage level, a second voltage level, and a third voltage level to the gate of the transistor device, wherein the first, second, and third voltage levels are distinct voltage levels. The disclosure further relates to a method of operating a transistor device that acts as a switch. The proposed circuit provides additional gate voltages, by contrast to conventional two-level gate drivers. By appropriate choice of the additional gate voltages, reverse mode conductance losses of the transistor device can be reduced and/or to the Safe Operating Area (SOA) of the transistor device can be improved.

Abstract: An object of this disclosure is to implement a Buck, Boost, or other switching converter, with a circuit to supply a reference voltage and Adaptive Voltage Positioning (AVP), by a servo and programmable load regulation. The reference voltage is modified, achieving a high DC gain, using a servo to remove any DC offset at the output of the switching converter. The correction implemented by the servo is measured, and a programmable fraction of the correction is injected back on either the reference voltage or the output feedback voltage. To accomplish at least one of these objects, a Buck, Boost, or other switching converter is implemented, consisting of an output stage driven by switching logic, with a servo configured between the reference voltage and the control loops of the Buck converter. The AVP function is implemented on either the reference voltage or output feedback voltage.

Abstract: The present document describes a digital power amplifier configured to provide an amplified output signal at an output port based on an input signal. The power amplifier comprises a drive unit configured to generate a high side drive signal comprising a sequence of pulses for controlling the high side switch and a low side drive signal comprising a sequence of pulses for controlling the low side switch, respectively. The drive signals are generated such that the pulses of the high side drive signal are non-overlapping with regards to the pulses of the low side drive signal, and such that the sequence of pulses of the high side drive signal and the sequence of pulses of the low side drive signal have a reduced fraction of energy from higher order harmonics compared to a sequence of rectangular shaped pulses.

Abstract: A flyback converter control architecture is provided in which primary-only feedback techniques are used to ensure smooth startup and detection of fault conditions. During steady-state operation, secondary-side regulation is employed. In addition, current limits are monitored during steady-state operation using primary-only feedback techniques to obviate the need for a secondary-side current sense resistor.

Abstract: Current in a switching converter is controlled using a current-mode hysteretic controller. The high-side switch (usually a PMOS) is turned off when the current in the coil exceeds a certain peak control current. The low-side switch (usually an NMOS) is turned off when the current in the coil falls below a certain valley control current. A current ramp is added to one of these control currents, either peak or valley. The current ramp is initiated by a reference clock signal, which has the effect of synchronizing the switching converter to the reference clock.

Abstract: A method of synchronizing the clocks of a master device and at least a first slave device which are connected on a wireless network. The method includes sending a scan command from the master device to at least the first slave device, setting the master device to a broadcast mode and broadcasting data, the broadcast data comprising a first time stamp; scanning the broadcasting data at at least the first slave device and resetting the clock of the first slave device using the first time stamp. In particular, but not exclusively, the present disclosure relates to synchronizing the clocks of two devices which are connected on a Bluetooth Low Energy (BLE) wireless network.

Abstract: A wired connection, such as USB-C, for charging a sink from a source, has a configuration channel and a power transmission channel. The presence of data on the configuration channel is used to determine that a cable has been disconnected from the power source. This charging system contains a capacitive power converter and a controller for controlling the capacitive power converter. There is also a configuration channel detector, which is arranged to detect the status of the configuration channel and to provide this status to the controller, so that the system can determine that the source has been detached from the bus when no configuration channel data is present.

Abstract: A digital voltage regulator and a method to regulate an output voltage at an output node based on an input voltage is presented. The regulator has a driver stage with N driver slices, with N>1. Each of the N driver slices can be activated or deactivated individually. A driver slice comprises a current source to provide an output current component to the output node, if the driver slice is activated. Furthermore, the regulator has a control unit to activate a number n of the N driver slices, based on a deviation of a feedback voltage from a reference voltage, where the feedback voltage is dependent on the output voltage.