Abstract: A light emitting diode (LED) circuit for preventing parasitic current flow through a first LED when the first LED is in an off state is described, where the parasitic current flow is a result of one or more parasitic capacitances, the LED circuit comprising the first LED, and a first current switch coupled to the first LED and arranged to enable a current flow through the first LED when the first current switch is in an on state, where the first current switch is arranged to discharge the one or more parasitic capacitances when the first current switch is in the on state.

Abstract: The present document relates to a level shifter circuit configured to transform an input voltage at an input of the level shifter circuit into an output voltage at an output of the level shifter circuit. The level shifter circuit may comprise a first switching element coupled between an output supply voltage and a positive output terminal, wherein a control terminal of the first switching element is coupled to a negative output terminal. The level shifter circuit may comprise a second switching element coupled between the output supply voltage and the negative output terminal, wherein a control terminal of the second switching element is coupled to the positive output terminal. The level shifter circuit may comprise a drive circuit configured to drive the control terminals of the first and the second switching element based on the input voltage at the input of the level shifter circuit.

Abstract: A carrier tape has at least two conductive rails affixed at opposite edges of the carrier tape. The purpose of the conductive rails is to provide power to smart labels mounted to the carrier tape for charging the batteries of each of the smart labels or transferring data to or from the smart labels. Holes are pierced into the conductive rails and the carrier tape to make a jagged edge at the backside of each hole in the carrier tape. The jagged edge of each of the holes of the conductive rail and the carrier tape on one layer connects with the conductive rail of the layer immediately adjacent. The smart labels are mounted to the carrier tape with an adhesive. A transport package holds a carrier tape which retains the smart labels and the conductive rails and is configured to transfer charging current or data to the smart labels.

Abstract: The present document relates to power converters with multiple feedback loops. The present document relates to a power converter with at least two feedback loops. The power converter may include a first error amplifier configured to generate a first error signal based on a first reference signal and a first feedback signal. The power converter may include a second error amplifier configured to generate a second error signal based on a second reference signal and a second feedback signal. The power converter may include a selector circuit configured to generate a selection signal by selecting the first error signal or the second error signal. The power converter may include a first clamp circuit configured to limit the first error signal to a first threshold value. The power converter may include a first threshold value generator circuit configured to generate the first threshold value dependent on the first error signal.

Abstract: A method and an apparatus for filtering a wireless signal by parsing a wireless signal transmitted from a surrounding wireless terminal so as to extract channel information of the surrounding wireless terminal in a MAC frame and performing adaptive filtering on the wireless signal.

Abstract: The clock input of a buck converter is delayed, preventing sub-harmonic oscillation. The function may be achieved by implementing a clock delay generation circuit, configured to delay a next clock pulse by an amount of time directly proportional to the most recent on time of the high-side switch for peak-mode current control, inversely proportional to the most recent on time of the low-side switch for peak-mode current control, inversely proportional to the most recent on time of the high-side switch for valley-mode current control, or inversely proportional to the clock minus the most recent on time of the high-side switch for valley-mode current control.

Abstract: A digital filter structure and related method of digital filtering are presented. The digital filter structure is arranged to receive one or more clocked input signals having a first clock rate, and which is driven at a second clock rate higher than said first clock rate. The digital filter structure has a plurality of delay elements and multiplexing circuitry arranged to selectively engage the delay elements such that, at every clock cycle of the digital filter structure, a filter operation is performed on a different stream of data. The disclosure can be applied in many different contexts. One particular implementation example is that of an adaptive noise cancellation (ANC) system using sigma-delta infinite impulse response filters. In this context the present disclosure minimizes latency and hardware implementation area by requiring only one filtering circuit for multiple channels of data to be filtered.

Abstract: A voltage selection circuit for selecting a voltage from a plurality of input voltages comprising a plurality of diodes, each diode having a first terminal coupled to one of the input voltages, and a current sensor configured to sense a current flow through each diode, wherein the selected voltage is dependent on the sensed current flow. In operation, the circuit functions as a comparator to detect the maximum among the input voltages. The comparator decision is used to close one or more of the power switches to ensure that the load is powered from the highest input voltage.

Abstract: A flyback converter is provided that dynamically adjusts a drain threshold voltage for a current cycle of a synchronous rectifier switch transistor based upon operating conditions in a previous cycle of the synchronous rectifier switch transistor. A differential amplifier drives a gate voltage of the synchronous rectifier switch transistor during an on-time of the current cycle so that a drain voltage of the synchronous rectifier switch transistor equals the drain threshold voltage during a regulated portion of the current cycle.

Abstract: A secondary-side control loop for a flyback converter is provided that generates a secondary-side control signal during normal operation using a compensator. In periods of significant load changes, the compensator is bypassed so that the secondary-side control signal is generated as an open-loop signal.

Abstract: Provided are a method for managing usage time of an IoT device, and an apparatus therefor. According to the disclosure, a method for managing usage time of an IoT device which flexibly controls a standby mode of an IoT device according to a user's selection, and which enables a user to select an operation method of a standby mode by using an application for minimizing power consumption of an IoT device, and an apparatus therefor are provided.

Abstract: A system in package is provided comprising an embedded trace substrate having redistribution layers therein, at least one passive component mounted on one side of the embedded trace substrate and embedded in a first molding compound, at least one silicon die mounted on an opposite side of the embedded trace substrate and embedded in a second molding compound wherein electrical connections are made between the at least one silicon die and the at least one passive component through the redistribution layers, and solder balls mounted through openings in the second molding layer to the redistribution layers wherein the solder balls provide package output.

Abstract: It is an object of one or more embodiments of the present disclosure to provide a single-inductor dual-output (SIDO), or single-inductor multiple-output (SIMO), Buck switching converter which can supply opposite polarity current to its outputs, through an inductor. It is a further object of one or more embodiments, when one output has an overshoot and the other output is below a reference, to enable discharging the overshoot output to the other output, resulting in a significant charge recycling and considerable increase in power efficiency. Still further, it is an object of one or more embodiments to improve output voltage ripple, as both outputs are being supplied at the same time, compared to prior art SIDO operation, where only one output is supplied for a given phase.

Abstract: A demodulation unit for recovering a transmitted symbol from a received signal that has been modulated using an MDPSK modulation scheme is described. The demodulation unit is configured to, for a current time instant, derive a current sample of a phase signal indicative of a phase of the received signal. Furthermore, the demodulation unit is configured to determine a set of discrimination signals for the current sample of the phase signal, based on the current sample of the phase signal and based on one or more previous samples of the phase signal for one or more previous time instants. In addition, the demodulation unit is configured to determine the transmitted symbol for the current time instant based on the set of discrimination signals.

Abstract: Methods, structures and computer program products for digital sample rate conversion are presented. An input digital sample with a first frequency is converted to an output sample with a second frequency. A sample rate conversion circuit is provided which provides an enhanced transposed farrow structure that enables an optimised trade-off between noise levels and computational complexity. Each output sample is derived by convolution of a continuous time interpolation kernel with a continuous time step function representing the input sample stream. In a sample rate conversion structure, there is a trade-off between the quality and the computational complexity. The quality is defined as a ratio between the (wanted) signal power and the (unwanted) noise power. The computational complexity may be defined as the average number of arithmetic operations that are required to generate one output sample. A higher computational complexity will generally lead to a higher power consumption and larger footprint.

Abstract: A molded interconnection substrate system in package is achieved comprising a molding compound having redistribution layers therein, at least one first active or passive component mounted on one side of the molded interconnection substrate and embedded in a top molding compound, at least one second active or passive component mounted in a cavity on an opposite side of the molded interconnection substrate wherein electrical connections are made between the at least one first active or passive component and the at least one second active or passive component through the redistribution layers and solder balls mounted in openings in the molded interconnection substrate to the redistribution layers wherein the solder balls provide package output.

Abstract: A circuit and a method for providing a switchable current linkage between a first terminal and a second terminal is presented. The circuit has a transistor switch and a charge pump circuit. An output node of the charge pump circuit is coupled to a control terminal of the transistor device, and an input node of the charge pump circuit is coupled to a predetermined voltage. The charge pump generates a boosted voltage. A drive circuit provides feedback control for the current flowing through the transistor. The drive circuit also controls the voltage magnitude at the input node of the charge pump circuit in accordance with the feedback control or to control a magnitude of a voltage at the control terminal of the transistor device in accordance with the feedback control.

Abstract: A panel type fan-out wafer level package with embedded film type capacitors and resistors is described. The package comprises a silicon die at a bottom of the package wherein a top side and lateral sides of the silicon die are encapsulated in a molding compound, at least one redistribution layer connected to the silicon die through copper posts contacting a top side of the silicon die, at least one embedded capacitor material (ECM) sheet laminated onto the package, and at least one embedded resistor-conductor material (RCM) sheet laminated onto the package wherein the at least one redistribution layer, capacitors in the at least one ECM, and resistors in the at least one RCM are electrically interconnected.

Abstract: A DALI interface is provided that includes a digital isolator having an input terminal and an output terminal. A DALI bus controlled by a master device controls a binary voltage state of a voltage rail. A DFET couples between the input terminal and the output terminal to control a voltage of the input terminal responsive to the control of the DALI bus by the master device. The digital isolator responds to the control of the input terminal voltage to drive a digital signal through an isolation barrier to control a voltage of the output terminal to control a slave lighting device.

Abstract: It is an object of one or more embodiments of the present disclosure to provide a Multiple-Inductor Multiple-Output (MIMO) switching converter to supply several different output voltages. The combination of this MIMO converter with a booster circuit supplies one or more individual cores with current that bypasses the parasitic network. The booster circuit has a wider bandwidth or a faster response when compared to the main MIMO switching converter. The MIMO booster circuit can supply a number of cores with only a single set of shared inductors. The main advantages include a lower component count and a reduced printed circuit board footprint to support multiple cores in a Multiple-Inductor Multiple-Output. The present disclosure makes use of the low duty-cycle of the power peaks and the low statistical likelihood of these peaks occurring for all cores simultaneously.