Abstract: A flyback converter is provided with a synchronous rectifier (SR) controller including a pulse linear regulator (PLR) charging path and an LDO charging path. The SR controller is configured to monitor the switching period and/or duty cycle of a power switch in the flyback converter to select between the PLR and LDO charging paths.

Abstract: A circuit arrangement comprising a first capacitor and a second capacitor which are arranged in series between a high potential and a low potential is described. The circuit arrangement comprises first power consuming circuitry which is arranged in parallel to the first capacitor. The first power consuming circuitry (113) consumes electrical power at a first voltage. The circuit arrangement comprises second power consuming circuitry which is arranged in parallel to the second capacitor. The second power consuming circuitry consumes electrical power at a second voltage, wherein a magnitude of the sum of the first voltage and the second voltage is smaller than an absolute difference between the high potential and the low potential. The circuit arrangement sets a voltage at the first capacitor in accordance to the first voltage and to set a voltage at the second capacitor in accordance to the second voltage.

Abstract: A LED lighting system, such as a dimmable LED lamp, that may simulate the performance of an incandescent bulb. LED strings of different colors may be connected to the output of a single LED driver that regulates an overall intensity of light produced by the LED lighting system. The color of the LED lighting system may be controlled by circuitry, such as one or more switches, that allocates current between the LED strings to change the color temperature of light emitted by the LED lighting system as the light intensity changes.

Abstract: A node that stores a charge is discharged in two phases, starting with a current controlled phase where a current mirror sink controls the current sunk from the node, and then moving to a second phase where a resistive discharge is provided. A pull down device such as a transistor switches from its saturation mode in the first phase to its linear mode in the second phase. a discharge circuit implementing this method provides optimized area and control for the discharge process as compared with approaches that rely solely on current mirroring or resistive discharging.

Abstract: A switching converter comprising a regulation circuit adapted to regulate an output value of the converter based on a ramp signal is provided. A feedback circuit adapted to control at least one of a delay and a slope of the ramp signal based on a parameter of the ramp signal is also provided. A method of regulating an output value of a switching converter is also presented.

Abstract: Circuitry for controlling a non-overlap time for a first switch and a second switch is described. Within a first state, the first switch is closed and the second switch is open, and within a second state, the first switch is open and the second switch is closed. The control circuitry has a first auxiliary switch and a second auxiliary switch. The control circuitry determines whether during a transition from the first state to the second state a current has flown through the serial arrangement of the first and second auxiliary switches. The control means adapts a non-overlap time between the first and second control signals for controlling a following transition from the first state to the second state, dependent on whether during said transition between the first and second states a current has flown through the serial arrangement of the first and second auxiliary switches.

Abstract: A two-stage multi-phase switching power converter operates its first stage during nominal operation responsive to a nominal clocking frequency and operates its second stage during the nominal operation responsive to a second-stage clocking frequency that is greater than the nominal clocking frequency. In response to an application of a load, the first stage temporarily increases its clocking frequency from the nominal clocking frequency and implements a fixed duty cycle.

Abstract: A synchronous buck converter is provided in which a replica transistor has its drain coupled to a drain of the low-side switch transistor. A current sensing amplifier drives a scaled current into the replica transistor such that the drain-to-source voltage of the replica transistor substantially equals the drain-to-source voltage of the low-side switch. The replica transistor is much smaller than the low switch transistor such that the replica transistor's on resistance is higher by a scale factor Kf as compared to the on resistance for the low-side switch transistor.

Abstract: An input buffer circuit providing an interface between integrated circuits having differing power supply voltage sources. A voltage reference generator that produces dual reference voltages employing a flipped gate anti-doped transistor. A receiver is connected to receive the first reference voltage and the second reference voltage and the input voltage signal from an integrated circuit operating with a low power supply and transmitting with the first voltage range. The receiver has a first comparator, a second comparator, and a latching circuit. The first comparator compares receive the input voltage and the first reference voltage and the second comparator compares the input voltage and the second reference voltage for determining the output state of the receiver. The output of the receiver provides the data output signal from the input buffer.

Abstract: A switching power converter is provided that transitions between output voltage modes over a delay period using at least one of an adaptive resistor and an adaptive reference voltage circuit.

Abstract: A switching power converter is provided with a power-on-reset (POR) circuit that discharges essentially no current until a power supply voltage exceeds a POR threshold voltage.

Abstract: A wearable biometric device includes a biometric sensor system adapted to measure a predetermined physiological property of a user's body at two or more different locations at the body surface and to provide for each such location an associated primary signal indicative of said measured physiological property. The device also includes a detector system adapted to detect a level of coupling of the biometric sensor system with the body at each of the locations and to provide for each of the locations an associated secondary signal indicative of said detected level of coupling and also includes a signal processing unit adapted to generate an output signal indicative of said physiological property as a function of the primary and secondary signals.

Abstract: A switching mode power converter circuit and a method are presented. The circuit comprises a first transistor switch and a second transistor switch coupled in series between an input voltage level and ground. There is a control circuit for controlling switching operation of the first transistor switch and the second transistor switch. There is a detection circuit for sensing a voltage at an intermediate node arranged between the first transistor switch and the second transistor switch, for deriving an indication of a slope of the sensed voltage, and for generating a switching control signal for the control circuit on the basis of the derived indication of the slope of the sensed voltage. The control circuit sets a first timing for activating the first transistor switch and/or a second timing for activating the second transistor switch on the basis of the switching control signal.

Abstract: In one or more embodiments, a method comprises comparing an output voltage for a multi-phase DC-DC switching power converter to a reference voltage to produce an error voltage. The method further comprises, for a first inductor, generating a first dual-ramp voltage signal having a first DC voltage level, and level-shifting the first dual-ramp voltage signal to form a second dual-ramp voltage signal having a second DC voltage level different from the first DC voltage level. Further, the method comprises switching on a first power switch coupled to the first inductor according to a duty cycle determined responsive to a comparison of the second dual-ramp voltage signal to the error voltage, where the level-shifting of the first dual-ramp voltage signal adjusts the duty cycle of the first power switch to balance a current in the first inductor with a current in a second inductor for the multi-phase DC-DC switching power converter.

Abstract: A circuit and a method for power conversion and for generating an output voltage in accordance with a reference voltage are presented. The power converter has a circuit for filtering the output voltage, an error amplifier circuit that compares the reference voltage and the filtered output voltage for generating an error voltage as a result of the comparison. There is a circuit for driving one or more switching devices in dependence on the error voltage. The error amplifier circuit has a first differential circuit and a first bias current generation circuit for generating a first bias current for the first differential circuit, a second differential circuit and a second bias current generation circuit for generating a second bias current for the second differential circuit, and a circuit for redistributing the first bias current to the second differential circuit or redistributing the second bias current to the first differential circuit.

Abstract: A multiphase power converter and a corresponding method is presented. The multiphase power converter contains a first and a second constituent switched-mode power converter. The first constituent switched-mode power converter provides, both in a first mode of operation and in a second mode of operation, a first phase current to an output of the converter. The second constituent switched-mode power converter provides, in the second mode, a second phase current to the output of the converter. The converter switches, depending on an operation condition of the converter, between the first mode and the second mode. A first transconductance of the first constituent switched-mode power converter is adapted when switching between the first mode and the second mode. By adapting the first transconductance, unsteadiness of the output voltage of the converter occurring during the switching between both modes of operation is minimized.

Abstract: An auto-calibrated current sensing comparator is provided. A secondary dynamic comparator shares the same inputs and acts to adjust a calibration control of the current sensing comparator. The calibration control may be in the form of adjusting the offset of the current sensing comparator or adjusting a propagation delay that is added to its output.

Abstract: A system is disclosed which allows for a multiphase Buck switching converter, where some phases operate in peak-mode current control, and some phases operate in valley-mode current control, simultaneously with the peak-mode phases. The peak-mode phases of the switching converter operate at lower frequency, and with a higher value inductor than the valley mode phases. The peak-mode phases support discontinuous control mode (DCM) operation and continuous control mode (CCM) operation, and the valley-mode phases only support CCM operation. The peak-mode phases of the switching converter are always enabled, and the valley-mode phases are only enabled at high currents. The peak-mode and valley-mode currents are matched with a peak current servo, for better efficiency.

Abstract: The proposed Power Management Integrated Circuit (PMIC) features the option to synchronize the charge-pump of a PMIC with the system clock, and then to swap and self-oscillate and skip pulses, when the digital controls of the PMIC send a first order to the charge-pump. The clock control circuitry of the PMIC also features the option for the charge-pump to then swap and use the system clock again, when the digital controls of the PMIC send a second order to the charge-pump. The designed transition of the clock from clock sync-mode to self-oscillate, and from self-oscillate back to clock sync-mode, does not present any phase discontinuity.

Abstract: A controller for a switching power converter is provided with a single detection pin through which the controller monitors whether the switching power converter is connected to an AC mains. Should a voltage for the detection pin indicate that the switching power converter is disconnected from the AC mains, the controller asserts the detection pin voltage to trigger a bleeder circuit to discharge an X class capacitor.