Abstract: Aspects of the invention include a method of conducting a reduced length search along a search path. A node which would otherwise occur between a previous and a following node in the search path is eliminated, and information is stored as to whether, had said eliminated node been present, the search would have proceeded to the following node. During the search, a search argument is compared with the stored information, and the search effectively progresses from the previous node directly to the following node if the comparison is positive. In preferred embodiments, some nodes provide result values for the search, and a node is eliminated only if its presence would not affect the result value for the search. In another aspect, the invention features a method of conducting a two mode search of reduced length. For a first mode of the search, nodes along a search path are provided, at least some of the nodes including one or more pointers pointing to other nodes.

Abstract: A novel scheduling method is provided which may be used for rate-based scheduling (e.g., for scheduling flows at some assigned rates in a computer network) or for weighted fair sharing of a common resource (e.g., scheduling weighted jobs in a processor). The method is based on hierarchical application of Relative Error (RE) scheduling. The present method of a Hierarchical RE Scheme (HRE) with complexity O(log(N)), where N is the maximum number of jobs supported by the scheduler, is provided.

Abstract: An electrostatic discharge protection device for protecting a mixed voltage integrated circuit against damage is provided which includes at least one pair of NMOS transistors connected in a cascode configuration. Each NMOS transistor pair includes a first transistor, having a drain region coupled to an I/O stage of the mixed voltage integrated circuit, and a gate region coupled to the mixed voltage integrated circuit's low power supply. The protection device also includes a second NMOS transistor, merged into the same active area as the first transistor, having a gate region and source region coupled to the ground plane of the mixed voltage integrated circuit. The drain region of the second transistor and the source region of the first transistor is constructed by a shared NMOS diffusion region. This shared diffusion region also constructs the common node coupling the source region of the first transistor to the drain region of the second.

Abstract: A method for improving the performance of a graphics system includes the steps of allocating appropriate pixels to slices of memory such that corresponding subsets of bits of neighboring pixels are allocated to different slices of memory, where `neighboring pixels` includes both consecutive pixels in a scan line, or pixels in consecutive scan lines. In addition, hardware is provided that allows for the individual memory slices to be independently accessed, thus allowed each slice to access data from a different 64 bit word in video memory during one video access period. Controllers which independently access the memory slices are advantageously totally time independent, to allow the most flexibility in the starting and finishing of the access of the memory slice. Performance is further gained by buffering of both the read and write requests to the video memory.

Abstract: A circuit board retainer for use within an enclosure for guiding and securing a circuit board within the enclosure includes a guide portion having an upper rail and a lower rail extending along an edge of the circuit board retainer forming a slot therebetween for guiding a side of the circuit board. A latching portion positioned adjacent to the guide portion engages an ejector lever pivotably connected to the circuit board. The ejector lever is capable of locking the circuit board in place relative to the circuit board retainer.

Abstract: In a computer implemented method, packets are transparently and securely communicated between a trusted computer and an untrusted computer connected by a gateway. Each packet including a source address, a destination address and a payload. The gateway, according to rules stored in a configuration database, intercepts a packet received in an Internet protocol layer of the gateway. The packet has a source address of the trusted computer, a destination address of the untrusted computer and a first payload. The intercepted packet is diverted to a proxy server operating in an application protocol layer of the gateway. The intercepted packet is consumed by the proxy server, and the proxy server generates a second packet having a source address of the gateway and the destination address of the untrusted computer and the first payload. The second packet is sent to the untrusted computer to enable the trusted computer to communicate with the untrusted computer securely.

Abstract: A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream.

Abstract: An arrangement for mounting a heat sink to a mounting board. The arrangement includes a heat sink and a locking member. The heat sink has a bottom surface and a passageway extending therein from an entrance opening on the bottom surface in a direction normal thereto and terminating with a closed end at its inner end. The passageway has an entrance region tapering toward the closed end and an inner region defined by generally parallel side wall portions. The side wall portions defining the entrance region including an engagement surface facing the closed end of the passageway. The locking member is T-shaped with the member crossing the stem of the T adapted for snug fit engagement with the generally parallel walls of the passageway's inner region. Moreover, the crossing member has an engagement member at each of it's ends that extend toward the base of the stem. The engagement members interlock with the engagement surface when the locking member is inserted into the passageway of the heat sink.

Abstract: A system and method for rapid panning of graphics images stored as objects in an object records database. The system comprises a computer with memory or memories divided into a several memory regions. The computer is coupled to a monitor for displaying graphics files stored in the database. The memory regions include: a virtual map (VMAP) region including cell maps comprising pointers to linked lists of objects in the database; a backing store region storing a bitmapped image of an entire file, and having the same effective dimensions as the VMAP; a main store region storing a smaller portion of the bitmapped image, the main store region having the same pixel dimensions as a viewing region on the monitor and a movable main store viewing window which permits a view of the subset of the bitmap.

Abstract: The variable-level backup scheduling method employs a schedule in which backups are performed at set times but the level of backup performed is determined from the condition of the system at the time of backup. Under this method, user-supplied parameters stored in level-tables allow a determination of the appropriate level of backup to be performed. If the data in the scheduled level of backup has not been modified in a sufficient amount under the supplied parameters, then the backup scheduling method determines whether a specified higher level backup is appropriate. If the evaluation of the higher level backup results in a determination that not enough data has been modified, the next level is evaluated. This process continues until the criteria for backup have been met or the level that has been predetermined to be the least amount of data to be saved has been reached.

Abstract: A method implemented by a computer network adapter for automatic retransmission of any packet involved in an unsuccessful transmission attempt due to transmit buffer underflow conditions entails the steps of (a) stopping the transmission; and (b) retrying another transmission of the packet for up to a predetermined number of attempts with an increased transmit threshold. The transmit threshold is the number of bytes of data of the packet involved in the transmission that are stored in the transmit buffer prior to start of transmission. Preferably, for the initial transmission attempt, the adapter requires only a small number of bytes of the packet to be stored in the transmit buffer. After occurrence of a buffer underflow condition, the adapter attempts a retry in accordance with the algorithm only after a substantially larger portion of the packet has entered the transmit buffer for transmission. If any retry succeeds, the adapter need not issue an interrupt.

Abstract: A method in accordance with the invention involves the normalization of a C language-type data structure received by a process in a distributed computing environment (DCE) to ensure that padding bits are consistently used. The method steps may advantageously be performed by a client process prior to and subsequent to a remote procedure call (RPC) to ensure that the padding bits are not undesirably changed as a result of the RPC. The method steps can also be performed by a server process to ensure that the structures it receives in RPCs are consistent in their use of padding bits. Normalization of the data structure permits a memcmp( ) or similar comparison function to be used to compare data structures without the risk that dissimilar padding bits will result in a false negative from the comparison.

Abstract: A language construct that allows a software programmer to use an intermediate or high-level language command to explicitly group operations or fuse loops in a group of statements operating on parallel arrays is disclosed. The command instructs a compiler, which would otherwise add temporary variables to avoid data dependencies or perform data dependency analysis, to translate the enclosed statements directly into machine language code without adding those temporary variables and without performing any data dependency analysis. Execution of the command results in the performance of the group of statements by all of the virtual processors.

Abstract: A modular front panel system for circuit cards utilizes hinged, interlockable, first and second circuit-card-carrying front panels. Each panel has a hinge component, e.g. a pivot element) that can mate with the component on the other panel (e.g., a groove). The hinged arrangement permits the panels to be releasably secured to one another so as to form a card assembly unit. The hinged arrangement also permits the panels to be moved angularly with respect to one-another, thereby facilitating assembly and disassembly of the two hinge components without obstruction by components mounted on the circuit cards. This is particularly well suited to applications in which the circuit cards have surface mounted connectors that mate and electrically connect when the panels are moved angularly. Moreover, the hinge arrangement permits a panel to be readily added and interlocked with, or removed from, an existing card assembly in electrical equipment, without requiring replacement of the existing front panel.

Abstract: Disclosed is a method and apparatus for reconstructing data in a computer system employing a modified RAID 5 data protection scheme. The computer system includes a write back cache composed of non-volatile memory for storing (1) writes outstanding to a device and associated data read, and (2) storing metadata information in the non-volatile memory. The metadata includes a first field containing the logical block number or address (LBN or LBA) of the data, a second field containing the device ID, and a third field containing the block status. From the metadata information it is determined where the write was intended when the crash occurred. An examination is made to determine whether parity is consistent across the slice, and if not, the data in the non-volatile write back cache is used to reconstruct the write that was occurring when the crash occurred to insure consistent parity, so that only those blocks affected by the crash have to be reconstructed.

Abstract: An apparatus and method of implementing an enhanced PCI interrupt controller which accommodates the industry standard wire-or functionality. With such an arrangement a method and apparatus to identify a source of a PCI interrupt without the need for polling is implemented with a register-based architecture and staged initiator decode. The invention implements both the default industry standard and a non-polled (interrupt accelerator) mode.

Abstract: A system and method and computer program product for encrypting data communications comprising the generation of a salt at a data transmitting system and combination of the salt with a primary encryption key known at the data transmitting system and a data receiving system. The salt and the primary encryption key are hashed to produce a transmitting encryption key and a data message is encrypted with an encryption function utilizing the transmitting encryption key to produce a ciphertext message. The salt and the ciphertext message are transmitted to the data receiving system where the salt and the primary encryption key are hashed to produce a receiving decryption key and the data message is retrieved by performing a symmetrical decryption function on the ciphertext message and the receiving decryption key.

Abstract: A jacketing system automatically interfaces dissimilar program units during program execution on a computer system. Means are provided for detecting a call for execution of a second program unit having a second call standard form a first program unit having a first call standard during execution of the first program unit on the computer system. A procedure descriptor is used in the code for the first program unit and it includes a signature that defines the call standard for each incoming call to the first program unit. A bound procedure descriptor is also used in the code for each outgoing call from the first program unit and it includes a signature that defines the call standard for the target program unit. Jacketing routines are driven by the descriptors in jacketing calls between the two program units.

Abstract: In a computer implemented method, a summary index data structure is generated from a data structure which indexes information stored in a database. Compressed word entries are written to a compressed index data structure. The word entries are written according to a collating order of the words which represent the unique portions of information of the database. Compressed location entries for each word entry are also written to the compressed index data structure immediately following each word entry. Each location entry indicates instances of the associated unique portions of the information represented by the words. While writing the word and location entries to the compressed index data structure, periodically sampling the location entries to generated summary entries. Each summary entry including an encoding of a last word entry written, an encoding of a last location entry written. Each summary entry also includes a pointer to the next entry following the sampled location entry.

Abstract: A computer implemented method selectively searches an index of a database according to scores assigned to records of the database located during the searching. The records of the database are index by storing index entries in a memory. Each index entry includes a word entry representing a unique portion of information of the database and one or more location entries indicating where the unique portion of information represented by the word entry occurs in the records of the database. A weight is assigned to each index entry according to a relative frequency of occurrence of the portion of information in the database. The index is sequentially searched to locate records qualified by a query having terms and operators. The terms correspond to index entries. The located records are scored according to the number of times portions of information corresponding to the terms of the query occur in the records and their associated weights.