Abstract: A computer implemented method searches an index to locate records of a database using an object oriented interface. Each record has a unique address in the database. The index is organized as a plurality of index entries where each index entry including a word and an ordered list of locations where the word occurs in the database. The words represent a unique piece of information of the database. The index entries are ordered first according to the collating order of the words, and second according to the collating order of the locations of each associated word. A query is parsed into terms and operators. Each term is associated with a corresponding index entry, the operators relate the terms. A basic stream reader object is generated for each term of the query. The basic stream reader object sequentially reads the locations of the corresponding index entry to determine a target location. A compound stream reader object is generated for each operator.

Abstract: A method is provided for estimating statistics of properties of instructions processed in a pipeline of a computer system, the pipeline having a plurality of processing stages. Instructions are fetched into a first stage of the pipeline. Some of the fetched instructions are randomly selected. State information of the system is recorded in a profile record as samples while the selected instruction are processed by the pipeline. The recorded state information is communiucated to software. The software statistically analyzes the recorded state information from a subset of the selected instructions to estimate the statistics of the instructions.

Abstract: A computer system including a cache which has a wave pipeline read controller is described. The system in addition to the cache memory includes a processor coupled to the cache memory. The processor includes a register stack which stores values corresponding to a wave number and read speed which is loaded as part of a configuration of the processor. The processor determines a repetition rate for read data corresponding to a difference between the values of read speed and wave number. The processor includes a logic delay line comprised of a plurality of clock delay elements, each of said elements providing successively increasing discrete delays to a clock signal fed to the logic delay line. The delay line is used to provide inputs to a first and second multiplexer which are respectively controlled by a signal corresponding to a desired repetition rate for read cycles and a signal corresponding to the read speed of the cache memory.

Abstract: A content addressable memory comprising a random access memory (RAM) including a plurality of data storage locations. Each of the data storage locations has a unique address. The content addressable memory operates to store a data entry comprising predetermined match information for at least a portion of a data entity. Each at least a portion of a data entity comprises the unique address of the respective data storage location. The RAM has an address port for input of at least a portion of a data entry as an address and an output for outputting the stored data entries. The RAM operates to fetch the data entry stored at the input address and to output the stored match information corresponding to the at least a portion of a data entity, in response to input of the at least a portion of a data entity as an address to the RAM. In a particular embodiment the RAM comprises an array of n RAMs, wherein the at least a portion of a data entity is segmented into n slices.

Abstract: In a computer implemented method, a client computer connected to a public network such as the Internet makes a request for an intranet resource to a tunnel of a firewall isolating the intranet from the Internet. The request is made in a public message. The tunnel sends a message to the client computer to redirect to a proxy server of the tunnel. The client computer send a token and the request for the resource the proxy server. If the token is valid, the request is forwarded to the intranet, otherwise, the user of the client computer must first be authenticated.

Abstract: In a computer system, a user interacts with a plurality of applications using natural language text provided by an input device. In order to enable the applications for user interaction, rules are registered on a blackboard of an arbiter. The arbiter can be localized, or distributed. Each rule is identified with a particular application, and can include a callback procedure. Each rule includes a left-hand side symbol and a right-hand side string which is a translation of the symbol. A parser parses a natural language input text string using the register rules to generate an evaluation tree. The evaluation tree is expressed in the form of an interpretive language. The evaluation tree is interpreted to produce at least one application request. The application request is generated by the callback procedure associated with a specific one of the rules applied during the parsing of the input text. The request is transmitted to the application identified with the applied rule.

Abstract: A parser for reading bits of a packet has a set of logic circuits implemented in a computer chip; a memory interacting with the computer chip, the memory providing first data to the set of logic circuits; means for reading bits from any field of packet into the set of logic circuits, the bits providing second data to the set of logic circuits; means, responsive to the first data and the second data, for the logic circuits to interpret bits of the packet.

Abstract: A computer system for executing a binary image conversion system which converts instructions from a instruction set of a first, non native computer system to a second, different, native computer system, includes an run-time system which in response to a non-native image of an application program written for a non-native instruction set provides an native instruction or a native instruction routine. The run-time system collects profile data in response to execution of the native instructions to determine execution characteristics of the non-native instruction. Thereafter, the non-native instructions and the profile statistics are fed to a binary translator operating in a background mode and which is responsive to the profile data generated by the run-time system to form a translated native image. The run-time system and the binary translator are under the control of a server process.

Abstract: An operation of a processor is traced while fetching instructions from a memory to operate the processor. The tracing involves detecting an unpredictable fetching of instructions on the assumption that a predictable fetching can be reconstructed without any further input. The unpredictable fetching is identified as being due to either computable, conditional, or unanticipated events. Upon detecting the events, process control information, such as the next instruction to be fetched is recorded in a queue, and from the queue the information can be stored in a trace buffer. During reconstruction of the operation, the trace buffer, and the image including the instructions can be examined to analyze the real-time operation of the processor.

Abstract: A method of conducting computerized commerce on a number of computer systems connected by a computer network including providing a broker computer system, the broker system having a database of broker scrips, each of the broker scrips representing a form of electronic currency, providing a vendor computer system, the vendor computer system having a database containing products which may be exchanged for the broker scrips, the vendor computer system capable of providing vendor scrips, providing a consumer computer system, the consumer computer system having a user interface wherein a user may initiate transactions in the consumer computer system to obtain one or more of the products contained in the database of the vendor computer system, sending a first request from the user on the consumer computer system to obtain a first broker scrip from the broker computer system, processing the first request in the broker computer system, sending the first broker scrip to the consumer computer system in response to the

Abstract: A method for translating a boolean function into a logic circuit using gates from a standard library is provided. The method includes the steps of translating the boolean function into a network comprising a plurality of sub-trees, where each of the sub-trees represents a portion of the function, and where each sub-tree includes a plurality of representations for that portion of the function. The plurality of representations are stored in an alterative logic diagram, which comprises a plurality of ugates. The ugates are data structures which define the inputs and the connectivity of the respective ugate in the sub-tree. The sub-tree is mapped to gates from the standard library by selecting the best sub-tree representation. Accordingly, an improved method of logic synthesis is provided that allows for the optimal representation to be provided by starting with a wider range of inputs to the mapping process.

Abstract: A method for translating a virtual address into a physical address, in which page tables used in the translation process are referenced by virtual addresses. Typically, a translation mechanism includes a translation buffer that, given a virtual address, can sometimes provide the corresponding physical address. A translation-buffer miss is said to occur when the translation buffer is presented with an address for which it can not provide the translation. When such a miss occurs, the translation mechanism obtains the translation by reading the page tables. When the translation mechanism attempts to read the page tables from virtual memory, a second-order miss can occur. The difficulty of infinite recursion of misses is avoided by handling second-order misses differently from first-order misses. When a second-order miss occurs, the translation mechanism uses a prototype page table entry and the virtual address of the page table entry to produce a physical address without using the page tables.

Abstract: A method for predictive prefetching of objects over a computer network including the steps of providing a client computer system, providing a server computer system, the server computer system having a memory, a network link to the client computer system, the network link also providing connection of the server computer system to the computer network, requesting from the server computer system by the client computer system a retrieval of a plurality of objects, retrieving the plurality of objects by the server system, storing the retrieval and an identity of the client computer system in the memory of the server computer system, sending the plurality of objects from the server computer system to the client computer system over the network link, predicting in the server computer system a plurality of subsequent retrieval requests from the client computer system according to a predetermined criteria, sending the prediction to the client computer system, and prefetching by the client computer system an object ba

Abstract: A cache memory system in a computing system has a first cache module storing data, a second cache module storing data, and a controller writing data simultaneously to both the first and second cache modules. A second controller can be added to also write data simultaneously to both the first and second cache modules. In a single write cycle each controller requests access to both the first and second cache modules. Both cache modules send an acknowledgement of the cache request back to the controllers. Each controller in response to the acknowledgements from both of the cache modules simultaneously sends the same data to both cache modules. Both of the cache modules write the same data into cache in their respective cache modules.

Abstract: In a distributed shared memory computer system a plurality of workstations are connected to each other by a network. Each workstation includes a processor, a memory having addresses, and an input/output interface connected to each other by a bus. The input/output interfaces connect the workstations to each other by the network. In a software implemented method for batching access checks to shared data stored in the memories, a set of the addresses of the memories are designated virtual shared addresses to store shared data. A portion of the virtual shared addresses is allocated to store a shared data structure as one or more lines accessible by instructions of the programs executing in any of the processors, the size of each line being a predetermined number of bytes. The programs are analyzed to locate a set of instructions of a particular program which access a range of target addresses storing shared data, the range of target addresses being no greater than the size of one line.

Abstract: In a computer system, an apparatus is configured to collect performance data of a computer system including a plurality of processors for concurrently executing instructions of a program. A plurality of performance counters are coupled to each processor. The performance counters store performance data generated by each processor while executing the instructions. An interrupt handler executes on each processors, the interrupt handler samples the performance data of the processor in response to interrupts. A first memory includes a hash table associated with each interrupt handler, the hash table stores the performance data sampled by the interrupt handler executing on the processor. A second memory includes an overflow buffer, the overflow buffer stores the performance data while portions of the hash tables are active or full. A third memory includes a user buffer, and means are provided for periodically flushing the performance data from the hash tables and the overflow to the user buffer.

Abstract: Information is stored in temporary storage and subsequently transferred to a memory over a bus. The temporary storage is provided with a plurality of entries each of which has a selected size that is smaller than a size of the bus. Information that is designated for a common area of the memory is stored in different entries, and the different entries are linked. Before being transferred to memory, the information from linked entries is assembled. The assembled information is then transferred over the bus to memory. Embodiments of the temporary storage include a write queue and a write buffer.

Abstract: A mechanism for operating a configurable switch to dynamically (i) route each of the data packets in an ordered string from a particular switch input port through a selected member output port of a hunt group; and (ii) route data packets which need not be transmitted in order from the input ports to available member output ports of the hunt group, as the members become available. A controller assigns each input port a service number, and directs member output ports to handle requests for ordered data packet transmissions from input ports with particular service numbers, such that the ordered transfers from an input port are handled by a single member of each group. The input port broadcasts, through the switch, a request to send ordered data packets through a particular hunt group and includes its service number in the request. The group member assigned to handle ordered transfers from the input port responds by identifying itself.

Abstract: An apparatus is described to provide a fault tolerant power-on of a computer system, using a BIOS memory containing a primary power-on system level configuration program for a computer system and a separate memory which contains a subset of the primary power-on system level configuration program. The subset program is accessed automatically, without human intervention, responding to a checksum detector of the BIOS memory data.