Abstract: A method and apparatus for configuring a computer system is presented. Underlying system software communicates information to a configuration utility. The information identifies a particular operating system that executes in the computer system. Using this information, the configuration utility formulates configuration filenames and retrieves data from the configuration files describing system resources, system device requirements, and operating system constraints. The configuration utility performs the system configuration by allocating system resources to system devices in accordance with the operating system constraints and system device requirements.

Abstract: A filler plate for filling an option card slot in a computer enclosure includes a cover plate portion for substantially covering the option card slot. The cover plate portion has a first end and a second end opposite to the first end. A tongue extends from the first end of the cover plate portion for insertion into a capture slot located in the enclosure adjacent to the option card slot to secure the first end of the cover plate portion to the enclosure. First and second retaining tabs extend substantially perpendicularly from the cover plate for engaging first and second edges of the option card slot to hold the filler plate in position relative to the option card slot.

Abstract: An interface module for an electronic system that permits signals to pass between a high frequency main circuit board area such as used for central processing units, memories, or other relatively high clock rate components and a low frequency circuit area such as used for standard peripheral circuit modules used for disk drives, video interfaces and the like. The interconnect module is positioned near an opening in a sheet metal bulkhead used as an electromagnetic interference (EMI) barrier around the main circuit area. The interface module uses a connector that is surrounded by one or more conductive shields that contain metal fingers on inboard and outboard sides to provide a ground connection between the interface module and the EMI barrier.

Abstract: Apparatus and a related method for managing entities in a complex and, in general, geographically distributed system, such as distributed data processing system. The management approach is defined in terms of a generalized model having management modules integrated into a single cooperative system by a management director kernel. The management modules include presentation modules to provide an interface with users who manage the complex system, access modules to provide an interface with managed entities or devices, and function modules to define various functions that may be performed in controlling or monitoring the managed entities. If the complex system being managed is large, a managed entity and an associated access module may be located on one physical system, while a presentation module is located on another physical system, close to the user, and a function module being used might be located on yet another physical system, for reasons of processing convenience.

Abstract: A field effect transistor structure having a first type conductivity semiconductor body disposed on an insulator and having formed in different regions of the semiconductor, a source region and a drain region of the opposite type conductivity to the first type, a gate electrode adapted to control a flow of carriers in a channel through the semiconductor body between the source and drain regions, and a Schottky diode contact region between the semiconductor body and one of the source or the drain regions. With such an arrangement, the Schottky diode, when forward biased provides a fixed voltage, about 0.3 volts, between the semiconductor body and one of the source or the drain regions.

Abstract: An object-oriented filter for an information stream includes an interface module to provide a common interface for accessing an application program and a filter module. The filter module uses suitable predefined functions to test the "tagged" fields of a current message from the information stream against filter rules and to determine the "actions" to be performed.

Abstract: A top-down clustering method and apparatus recursively processes clusters of documents by first extracting features from the documents comprising the cluster, then using the extracted features to generate sub-clusters and finally using the generated sub-clusters to develop topics and identifiers for each sub-cluster. This process is repeated for each cluster and sub-cluster in a recursive manner so that clustering is performed using features extracted from each document in a cluster to perform sub-clustering. Feature extraction is performed by using frequency counts of terms taken from each document in a cluster and discarding terms falling outside of predetermined boundaries computed based on the total number of documents in the cluster. After bounding, the number of tokens is reduced prior to clustering by means of a correlation technique, such as a PCA model.

Abstract: A printer architecture utilizing network resources to distribute printer controller and translator functions and thereby process several print jobs in parallel. The several print jobs can be transferred, in order of completion, to a print engine for a high speed real time printing operation, or stored as pre-rasterized images for subsequent access and delivery to the print engine.

Abstract: A data base is created by storing a plurality of data objects in a memory. Each data object has attributes including a key value and a data value. The data objects are partitioned into a plurality of classes, each class having one or more members, each member including the same attributes of the data objects. An access method is defined for at least one member of a specific class to access the data objects of the specific class by key values. For another member of the specific class, an access method to access the data objects of a related class is defined. A specific data value of a specific data object is compared with the key values of the data objects of the related class, and if the specific data value is equal to the key value of a related data object a memory address of the related data object is associated with the specific data value.

Abstract: A method executed in a computer system for detecting and handling an invalid use of a data structure is described. The method includes the steps of providing a data structure associated with a first computing environment. The data structure includes a field having a value stored therein identifying an inaccessible address in a second computing environment. This field is used in detecting an invalid use of the data structure in the second computing environment by a computer program attempting to access memory using said inaccessible address indicated by said value contained in the first field. Additionally a preferred data structure is described as are alternative embodiments of detecting an invalid use of a data structure.

Abstract: A graphical figure is defined. A library of simple tasks is created using trial stimulus/response combinations. A hill climbing algorithm is employed to find a stimulus/response combination that accomplishes an optimum result for each task. An animation editor facilitates the creation of composite animated sequences by causing the retrieving and displaying of a first simple task, controlling the length of time the first simple task is displayed and by causing the retrieving and displaying of additional simple tasks and controlling the length of time the additional simple tasks are displayed.

Abstract: A new class of purpose computers called Programmable Reduced Instruction Set Computers (PRISC) use RISC techniques a basis for operation. In addition to the conventional RISC instructions, PRISC computers provide hardware programmable resources which can be configured optimally for a given user application. A given user application is compiled using a PRISC compiler which recognizes and evaluates complex instructions into a Boolean expression which is assigned an identifier and stored in conventional memory. The recognition of instructions which may be programmed in hardware is achieved through a combination of bit width analysis and instruction optimization. During execution of the user application on the PRISC computer, the stored expressions are loaded as needed into a programmable functional unit. Once loaded, the expressions are executed during a single instruction cycle.

Abstract: The present invention is a method of writing data to a storage system using a redundant array of independent/inexpensive disks ("RAID") organization that eliminates the write hole problem of regenerating undetected corrupt data. The invention also overcomes the need for system overhead to synchronize data writes to logical block numbers that map to the same parity block. A log is constructed and used for storing information relating to requested updates or write operations to the data blocks in the multiple disk array. A separate entry is made in the log for each parity block that must be updated as a result of the write operation. Each log entry contains the addresses of the logical block numbers to which data must be written for that operation. After the new data is written to data blocks in the RAID array, a background scrubber operation sequentially reads the next available entry in the log and performs a parity calculation to determine the parity resulting from the write operation.

Abstract: A locking mechanism for facilitating connection between a first housing and a second housing. The locking mechanism mounted in the mounting region of the second housing and includes a plunger mounted for movement up to an extended position, a biasing device urging the plunger toward the extended position, a catch spring, and a release button having a ramp, such release button being mounted on the second housing for back and forth movement in a direction transverse to the direction of the plunger and along a path that brings the ramp into contact with the catch spring when the release button is moved forward.

Abstract: Method and apparatus for operating a multiprocessor data processing system (10) of the symmetric multiprocessor (SMP) type so as to continue the execution of a process running on a failed CPU (CPU-F). In response to a failure of one of the CPUs a first method performs the steps of: detecting that one of the CPUs has failed during the execution of a first process; extracting an internal processing state from the CPU-F; inserting the extracted processing state into a second, recovery CPU (CPU-R); and completing the execution of the first process with the CPU-R. During the time that the CPU-R executes the first process the CPU-R assumes the identity of the CPU-F, and furthermore assumes the ownership of any spinlocks that may have been owned by CPU-F. If selected from an active set of CPUs the operation of the CPU-R may be timeshared between the first process and a process that is running in the CPU-R.

Abstract: An apparatus is provided to reduce the amount of EMI generated by a circuit. The grounding of an enclosure is improved by providing a number of shaped protuberances, the protuberances having an end that penetrates a conductive region of a circuit board, such that when the circuit board is mounted to the support member, the protuberances make a penetrating electrical contact and provides for additional ground paths, thereby reducing the EMI generated by the assembly.

Abstract: A digital phase lock loop synchronizes a first signal to a second signal having a predefined frequency. The first signal usually has an instantaneous frequency greater than the predefined frequency, so that the first signal is constantly gaining phase with respect to the second signal. The digital phase lock loop performs periodic correction cycles by detecting a predefined phase relationship between the first signal and the second signal, and when the predefined phase relationship is detected, expanding the first signal in phase by a predetermined amount. Preferably, the first signal is generated by clocking a frequency divider with a clocking frequency, and the first signal is expanded in phase by inhibiting the clocking of the frequency divider for one clocking cycle for each correction cycle. Preferably, the predetermined phase relationship is detected when the second signal has a predetermined logic state coincident with clocking by the clocking signal and a predetermined state of the frequency divider.

Abstract: A new security system including a plurality of inspectors each of which performs a security check operation in connection with a particular class of possible security violation conditions. One inspector detects security violation conditions reflecting selection of passwords using easily-guessable formatives. Another inspector detects security violation conditions reflecting ability of a network node to improperly use another node over a network. A third inspector determines whether the operating system files have satisfactory protection. Finally, a fourth inspector determines whether security violation conditions arise in connection with applications programs. If, during a security check operation, an inspector determines that a security violation condition exists, it records the condition in a common working memory for further reporting or analysis.

Abstract: A computer system with multiple execution boxes operates by assigning serial numbers to each instruction in a set of linearly dependent computer instructions and then rearranging those instructions into a set of instructions which are no longer linearly dependent. The original serial numbers assigned to each instruction are retained with the instructions after rearrangement. The serial numbers allow reconstruction of the original set of instructions from the rearranged set of instructions. Once rearranged, additional information is added to subsets of the rearranged set of instructions. The additional information allows several instructions to be executed in parallel while producing the same results as would have been produce had the instructions been executed one at a time by a sequential processor.

Abstract: A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. Macroinstruction pipelining is employed (instead of microinstruction pipelining), with queuing between units of the CPU to allow flexibility in instruction execution times. A wide bandwidth is available for memory access; fetching 64-bit data blocks on each cycle. A floating point processor function is integrated on-chip, with enhanced speed due to a bypass technique; a trial mini-rounding is done on low-order bits of the result, and if correct, the last stage of the floating point processor can be bypassed, saving one cycle of latency.