Abstract: A small bimetallic thermocouple probe device for use in scanning atomic force microscopy is mass produced by etching and oxidatively sharpening silicon points on a standard silicon wafer. The sharpened points are oxidized and the first thermocouple metal layer is deposited and patterned. The intermetal dielectric layer is deposited and removed in the area of the tip of the probe by a simple double spin photoresist process having a drying cycle between the two spins. The exposed tips have the dielectric etched, and the second thermocouple metal is deposited and patterned. The finished thermocouples are produced by etching the silicon from the back side of the wafer to free up the cantilevered structure which the probe are constructed upon. With such a procedure, large numbers of tiny, low thermal mass scanning atomic force microscope thermocouple probes may be inexpensively manufactured.

Abstract: The invention is a system providing adaptive stream buffers using instruction-specific prefetching avoidance (ISPA). According to the invention, each time the CPU executes an instruction resulting in prefetched cache lines not being used, the instruction address is stored in a table. Subsequent instruction addresses are compared to the instruction addresses in the table, and a stream buffer is not allocated when the subsequent instruction address is found within the table.

Abstract: A method and apparatus for transferring data units between a host memory and a peripheral interface, the data units being subject to a flow control mechanism whereby some of said data units are flow controlled and some of said data units are not. Two transmit buffer memories are coupled to the peripheral interface; one for storing controlled data units to be transferred to the peripheral interface and the other for storing uncontrolled data units to be transferred to the peripheral interface. A single request buffer stores successive requests for data to be transferred from a host memory to either of the two transmit buffer memories. Data transfer circuitry transfers data from the host memory to either of the two transmit buffer memories in response to the requests stored in the request buffer.

Abstract: A method for generating test cases for testing integrated circuits which comprises the step of apportioning a plurality of instructions into a plurality of groups of test instructions. At least some of the plurality of groups include a plurality of control flow instructions each of which transfer execution to a different one of the plurality of groups. This method prevents a test of an integrated circuit from entering an infinite loop.

Abstract: A method and apparatus for monitoring a physical process comprising a plurality of interacting attributes where the attributes are components of the physical process. The method and apparatus locates defective attributes and defective interactions between interacting attributes within the physical process. The apparatus comprises a processor, and input member and a hierarchical data structure. Data concerning the attributes of the physical process are input and organized into the hierarchical data structure. A response variable and a variation in the response variable for each population in the hierarchical data structure is determined, and used to identify defects in the physical process.

Abstract: An adjustable filter for a computing system having memory error detecting and correcting features selectively masks user-specified errors, thereby preventing storage of such errors in a control and status register (CSR). The invention includes a command and data register 102; a CSR 103; an error detecting and correcting circuit 108, including a check bit generator 108a, an error detecting circuit 108b, and an error correcting circuit 108c; a memory module 114; and filter logic 300. The contents of a filter control register 220 of the CSR 103 operate to specify a particular error which is to be "filtered". The filter logic 300 includes a plurality of logic gates that compare the user-specified signals stored in the register 220 with error-related signals reported by the error detecting circuit 108b. If the signals match, information associated with the detected error is prevented from being stored in the CSR 103.

Abstract: A system and method for automatically mapping on a computer display a graphical representation of a physical arrangement of a plurality of computer components in one or more cabinets, each cabinet having one or more shelves for housing the computer components. The status of the components is periodically monitored and the computer display updated accordingly. A graphical user interface is provided for user observation of the physical arrangement and status of computer components in the cabinets, as well as user control of the operational parameters of the components.

Abstract: In a distributed network, client computers are connected to server computers. The server computers store a plurality of Web pages. The Web pages are partitioned into sets, where each set includes Web pages that are substantially similar in content. A preset compression dictionary is generated for each set of Web pages. In addition, a fingerprint is generated for each preset dictionary. The fingerprints uniquely identify each of the preset dictionaries. When one of the client computers requests one of the Web pages, a compressed form of the Web page is sent along with the fingerprint of the dictionary that was used to compress the Web page. The client computer can then request the preset dictionary in order to decompress the Web page when the client does not have a copy of the preset dictionary.

Abstract: A prediction mechanism for improving direct-mapped cache performance is shown to include a direct-mapped cache, partitioned into a plurality of pseudo-banks. Prediction means are employed to provide a prediction index which is appended to the cache index to provide the entire address for addressing the direct mapped cache. One embodiment of the prediction means includes a prediction cache which is advantageously larger than the pseudo-banks of the direct-mapped cache and is used to store the prediction index for each cache location. A second embodiment includes a plurality of partial tag stores, each including a predetermined number of tag bits for the data in each bank. A comparison of the tags generates a match in one of the plurality of tag stores, and is used in turn to generate a prediction index.

Abstract: A multiprocessor having improved bus efficiency is shown to include a number of processing units and a memory coupled to a system bus. Also coupled to the system bus are at least one I/O bridge systems. A method for improving partial cache line writes from I/O devices to the central processing units incorporates cache coherency protocol and an enhanced invalidation scheme to ensure atomicity which minimizing the bus utilization. In addition, a method for allowing peer-to-peer communication between I/O devices coupled to the system bus via different I/O bridges includes a command and address space configuration that allows for communication without the involvement of any central processing device. Interrupt performance is improved through the storage of an interrupt data structure in main memory. The I/O bridges maintain the data structure, and when the CPU is available the interrupts can be accessed by a fast memory read; thereby reducing the requirement of I/O reads for interrupt handling.

Abstract: In a distributed shared memory system, clusters of symmetric multi-processors are connected to each other by a network. Each symmetric multi-processor includes a plurality of processors, a memory having addresses, and an input/output interface to interconnect the processors. A software implemented method enables data sharing between the clusters of symmetric multi-processors using variable sized quantities of data called blocks. A set of the addresses of the memories are designated as virtual shared addresses to store shared data, and a portion of the virtual shared addresses are allocated to store a shared data structure as one or more blocks. The size of a particular allocated block can vary for different shared data structures. Each block includes an integer number of lines, and each line includes a predetermined number of bytes of shared data. Directory information of a particular block is stored in the memory of a processor designed as the home of the block.

Abstract: In order to provide a thermal coupling between a heat source and a heat sink, an integrated interleaved-fin connector is provided. A first substrate includes a first side surface and a second side surface. A plurality of heat generating devices are formed in the first side surface. A plurality of first channels are etched in the second side surface to form a plurality of first fins. A second substrate has a plurality of second channels etched therein to form a plurality of second fins and a base. The base is for thermally engaging with a heat sink. The first and second fins providing a thermally conductive path from the heat generating devices to the heat sink when interleaved with each other.

Abstract: A method for communication includes transmitting a first datum using an electromagnetic wave of a first wavelength, and, while transmitting the first datum, detecting an energy level of an electromagnetic wave of a second wavelength. A collision is declared if the energy level of the second wavelength exceeds a threshold value.

Abstract: Video data representing a scene are processed to improve encoding efficiencies. The video data are segmented into rigidly and non-rigidly moving video objects. The segmentation is preformed by estimating local motion vectors for the video data of a sequence of frames. The local motion vectors are clustered to determine dominant motions, and video data having motion vectors similar to the dominant motions are segmented out as rigidly moving video objects. For these objects, motion parameters are robustly estimated. Using the motion parameters, the rigid video objects of the frames are integrated in one or more corresponding sprites stored in a long-term memory. The sprites can be used in a two-way motion compensated prediction technique for encoding video data where blocks of video data are encoded either from sprites based on rigid motion parameters, or from a previous frame based on local motion parameters.

Abstract: An apparatus for generating control signals of a microprocessor includes a memory, for example, a pattern holding register storing an arbitrary bit pattern. The holding register can be loaded by software. A shift register is connected to receive the bit pattern from the pattern register. An output pin of the microprocessor receives each bit of the arbitrary bit pattern, directly, or indirectly via a bus interface unit, at a rate determined by a clock signal to generate control signals for arbitrary external devices.

Abstract: A bracket for mounting a sliding fixture to a computer cabinet for enabling a computer to slide relative to the computer cabinet includes a bracket body portion having first and second ends. A first pattern of holes is formed through the bracket body portion enabling the bracket to be mounted to the sliding fixture with fasteners. A first flange portion extends from the first end of the bracket body portion at an angle relative to the bracket body portion. A second pattern of holes is formed through the first flange portion. A second flange portion extends from the second end of the bracket body portion at an angle relative to the bracket body portion. A third pattern of holes is formed through the second flange portion.

Abstract: A method to reduce the rate of interrupts by the central processing unit (CPU) without any loss of interrupts. The method uses two parameters. The first parameter sets the event threshold, which is the maximum value of consecutive events allowed to occur, for example, the maximum number of received data packets before an interrupt is posted (for example, a receive interrupt) to the CPU. The second parameter sets the event time-out, which is the maximum time an event can be pending before posting an interrupt to the CPU. The second parameter is needed since the flow of events in the system is unpredictable and without the time-out limit handling of the event can be delayed indefinitely.

Abstract: Computer method and apparatus for allocating and accessing large memory. Under a given operating system, the invention apparatus creates multiple processes, each having a corresponding virtual memory space allocated to the process. The generated virtual memory spaces allocated for the created processes are aggregated together to form a single working memory area. An index member cross references the formed working memory area relative to the created processes. As a result, the index member enables access to the generated virtual memory spaces collectively as though they were a single large working memory area.

Abstract: In a SCSI subsystem having mixed wide and narrow SCSI devices installed, a method and apparatus is provided for detecting a narrow SCSI device illegally installed at a slot assigned to a wide SCSI device. To detect the narrow SCSI device installed at an illegal location, high ID and low ID SCSI bus address pairs are set as test pairs for the SCSI subsystem. The low ID is the alias of the high ID if a narrow SCSI device is installed at the high ID slot. To detect a conflict with a controller ID, a non-responsive ID bus address corresponding to a slot known to be unused is called. A response to this call indicates a narrow SCSI device is installed at the high ID of the test pair and the narrow SCSI device at the high ID has configured to an alias bus address matching the controller ID. To detect a present conflict between SCSI devices, the low ID bus address in the test pair is called.

Abstract: In a computerized method, a computer program is analyzed while the program is interpreted. The program is expressed in a first memory as input values and functions. Some of the input values are complex values which can have a plurality of component values. Each function operates on combinations of the input values and the functions of the program. The program is interpreted in a processor connected to the first memory. The processor is also connected to a second memory to store result values produced during the interpretation. Selected input values, components of the complex values, and functions are named only if the selected values, components, and functions are necessary to produce a selected result value. For each function of the program, the function which is interpreted, the input values on which the function depends, and the result value produced by the function during interpretation, are recorded in the second memory to dynamically perform a precise dependency analysis of the program.