Abstract: A method and apparatus is presented for video image compression using a unique operand decomposition technique combined with an innovative data scatter and retrieve process. This combination of features allows the use of single ported RAM structures where multiported RAMS would normally be used, such as when retrieving two operands in the same time cycle. As applied to the Discrete Cosine Transformation this method and apparatus additionally allows elimination of the usual prior art use of a separate transpose matrix buffer. The elimination of the separate transpose matrix buffer is accomplished by combining the transpose matrix intermediate results memory storage with the memory buffer used for the other intermediate results in a double buffer system.

Abstract: A system for indexing stored information includes a processor and memory. The processor parses the information into indexable words. Each word represents either a portion of the information or an attribute of one or more portions of the information. The memory stores index entries. Each index entry includes a word entry representing a unique one of the words, and one or more location entries indicating a location of the unique word within the information.

Abstract: If the exponents of a floating-point-processor addition pipeline's input operands are equal, a signal (INVERT) that determines whether the pipeline's sole full-width carry-propagate mantissa adder (34) will invert one of its inputs results from an inversion-determination circuit (FIG. 11) that determines whether the sole set bit in a decoded normalization-shift signal (NORM.sub.-- SHIFT) occupies the same position as a set bit in a signal (FRAC.sub.-- A.sub.-- GT.sub.-- B) representing what the possible normalization amounts will be if a first of the mantissas is greater than the other, second mantissa. Consequently, a bit-comparison operation (56) that employs no full-width carry-propagate addition can determine the amount of normalization shifting to be performed by bit shifters (30 and 32) disposed in respective processing trains that generate mantissa inputs to the mantissa adder (34).

Abstract: Multicast addresses on a computer network are dynamically assigned to a temporary node task. In particular, a server dynamically assigns a multicast address to a data stream in response to a request for the data stream from a client. The server assigns the multicast address in cooperation with other servers from a pool of network-allocated but unassigned multicast addresses. Once the data stream is terminated, the assigned multicast address is deassigned and returned to the pool of unassigned multicast addresses for possible reuse by the nodes.

Abstract: A computer implemented method for generating a compressed index of information. The information is stored as a plurality of records in a database. Indexable portions of information are sequentially parsed to generate words and metawords. The words represent the portions, and the metawords represent attributes of the portions. A location is sequentially assigned to each word and metaword in the order that the portions are parsed to form pairs. The pairs are sorted first according to the words and metawords, and second according to the locations. Index entries are written to a memory for each unique word and metaword. Each index entry includes a word entry or a metaword entry, and one or more location entries. The word and metaword entries use a prefix encoding which indicates the number of bytes that the unique word or metaword of a next index entry has in common with the unique word or metaword of a previous index entry. The location entries use a delta value encoding.

Abstract: Techniques used in program development using a grammar sensitive editor are described. Input within an edit buffer is processed by a lexical and syntax analyzer in response to various syntactic and lexical states. Actions such as updating various multimedia indices are performed. Users are guided through program development through prompts for menu selection. The items transmitted on the menu are in accordance with the current state of lexical and syntactic processing. If an input in the edit buffer is invalid, the erroneous text is detected via the lexical and syntax analyzers and the erroneous text is highlighted. Additionally, transmitted via the menu is a selection of correct and valid alternatives from which the user may select to be included in the edit buffer.

Abstract: In a computer system, a data structure is provided in memory for storing one or more data files from an external device. The data files stored in the data structure are accessible by a number of processes executing in the computer system. The computer system includes a storage device such as a cache for storing data from a subset of pages of the memory. Each of the pages of the cache is referred to as a cache page, having an associated cache page address. A physical address is allocated for storing each page of a retrieved data file stored in the data structure such that a cache page address portion of the physical address is selected from the available cache page addresses. The physical address is further selected such that the cache page addresses are substantially evenly distributed amongst the pages of the retrieved data file and the data structure in order to minimize thrashing in the cache and enhance performance.

Abstract: A method for mapping a digitized image of a face to a wireframe is provided. The wireframe is composed of a plurality of nodes connected by lines. The method includes the steps of detecting a plurality of facial features from the plurality of pixels of a reference facial image. Corresponding facial landmark nodes in the wireframe topology are determined. A transform between the facial features and the landmark nodes is computed to map the wireframe topology to reference facial image. The reference facial image and a target facial image are cropped using a bounding box. The cropped reference facial image is registered with the cropped target facial image to determine a displacement field. The displacement field is applied to the mapped wireframe topology for the reference facial image to map the target facial image to the wireframe topology.

Abstract: An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory.

Abstract: An optical transceiver for transceiving optical signals in an optical LAN includes a first transceiver that detects and transmits the optical signals, a second transceiver that detects and transmits the optical signals, a control coupled to the first and second transceivers, the control transferring information carried by the optical signals between the transceivers, a power storage coupled to the control, and to the transceivers, and a photovoltaic cell coupled to the power storage for replenishing its power.

Abstract: A technique for controlling a power supply involves receiving a programming signal that indicates a power supply output voltage limit, activating the power supply such that the power supply provides a power supply output voltage according to a power supply threshold voltage, generating a tracking signal that tracks the programming signal, and generating a compare signal according to the tracking signal and an actual value of the power supply output voltage. The technique further involves comparing the compare signal to a protection threshold voltage, maintaining activation of the power supply when the compare signal is less than the protection threshold voltage, and deactivating the power supply when the compare signal is greater than the protection threshold voltage. The protection threshold voltage is independent of the power supply threshold voltage.

Abstract: A set of conductive plates are positioned adjacent to and in close proximity with a unidirectional heatsink on a high frequency integrated circuit. The set of plates is generally electrically attached to the same ground potential voltage supply as the integrated circuit and serves to damped unwanted radio frequency electromagnetic radiation normally emitted by heatsinks. The same arrangement of plates can also serve as an external electromagnetic interference shield apparatus for the integrated circuit. The plates may alternatively be comprised of a conductive mesh to allow air flow through the plates.

Abstract: An apparatus for displaying documents on a computer controlled display device provides a method for clipping. To clip a document is to restrict the viewable area of the screen object on the computer controlled display device associated with the document. A workspace viewer process maintains the documents in a three-dimensional virtual workspace. A document renderer and attribute-value pairs accomplish clipping in the virtual workspace. Clip stops constrain the clipping edges of a document so that the document may be clipped only to a specified set of positions.

Abstract: A memory controller for optimizing direct memory access (DMA) read transactions wherein a number of cache lines are prefetched from a main memory as specified in a prefetch length field stored in a page table. When all prefetch data has been fetched, the memory controller waits to determine whether the initiator of the DMA read transaction will request additional data. If additional data is needed, additional cache lines are fetched. Once the initiator terminates the DMA read transaction, the prefetch length field for a selected page other entry in the table is updated to reflect the actual DMA read transaction length. As a result, an optimum number of cache lines are always prefetched thereby reducing the number of wait states required.

Abstract: A multiprocessor having improved bus efficiency is shown to include a number of processing units and a memory coupled to a system bus. Also coupled to the system bus are at least one I/O bridge systems. A method for improving partial cache line writes from I/O devices to the central processing units incorporates cache coherency protocol and an enhanced invalidation scheme to ensure atomicity which minimizing the bus utilization. In addition, a method for allowing peer-to-peer communication between I/O devices coupled to the system bus via different I/O bridges includes a command and address space configuration that allows for communication without the involvement of any central processing device. Interrupt performance is improved through the storage of an interrupt data structure in main memory. The I/O bridges maintain the data structure, and when the CPU is available the interrupts can be accessed by a fast memory read; thereby reducing the requirement of I/O reads for interrupt handling.

Abstract: A document management apparatus provides a user to define delimiters in order to specify portions of documents or attributes of documents to be retrieved from a document repository. The repository is searched for the defined delimiters and the portions of the documents or the attributes of documents are retrieved and put into a cache memory. The user-defined delimiters may be multi-character delimiters. The cache memory and the document repository may be connected over a network.

Abstract: A boot strap assignment system is disclosed for a symmetric multiprocessor computer in which the role of the boot strap processor is assigned to one of the working processors by a central agent as part of power-on configuration. The system includes a system management processor which monitors the operation of the multiprocessor computer and controls a switching circuit that selectively transmits the boot strap assignment signal from the central agent to the working processors. Since the management processor monitors environmental conditions and shut-down events, it can predict the failure of working processors and assign the bootstrapping function appropriately. A watch dog timer is also provided in case the bootstrapping fails so that another working processor can be assigned the task of booting up the computer.

Abstract: A hands-free navigation system for tracking a head and responsively adjusting the display of a virtual reality environment includes a camera, the camera employed to follow movements of the head, a computer system connected to the camera, the computer system including a memory, a central processing unit (CPU), a digitizer, the digitizer providing a current image of a face of the head, a face tracker, the face tracker including the capability of receiving a reference face image from the digitizer, of receiving the current face image from the digitizer, of determining a head translation and orientation, and of providing the head translation and orientation to a three dimensional virtual environment viewer connected to the computer system for display of the virtual environment at the desired viewpoint.

Abstract: In a computerized method, performance data collected while a computer system executed instructions of a program are analyzed. The method collects performance data while executing the program. The performance data includes sample counts of instructions executed. The program is analyzed to determine classes of instructions. Instructions of the same equivalence class all execute the identical number of times. The execution frequencies for each instructions of each equivalence class is estimated. The estimated execution frequencies can then be used to determine the average number of cycles required to issue each instruction of each equivalence class. The average number of cycles can be compared with the minimum number of cycles to determine the number of dynamic stall cycles incurred by the instructions. Furthermore, reasons for the dynamic stall cycles can be inferred.

Abstract: A computer implemented method detects concurrency errors in programs. Machine executable images of multiple program threads are instrumented to locate and replace instructions which affect concurrency states of the threads. Concurrency state information is recorded in a memory while the multiple threads are executing. The recorded concurrency state information is analyzed, and inconsistent dynamic concurrency state transitions are reported as concurrency errors.