Abstract: A computer implemented method for down-loading mail messages in a distributed computer system. The distributed mail service system includes a plurality of client computers connected to a mail service system via a network. Mail messages are stored in message files of the mail service system, a particular mail message includes a primary component encoded in a first format, and at least one secondary component encoded in a second format different than the first component. The particular mail message is requested by a particular one of the plurality of client computer systems. The secondary component is replaced with a hot-link. The primary component and the hot-link are sent to the particular client computer.

Abstract: A technique for implementing a programmable thermal model of an integrated circuit component such as a central processing unit (CPU) and its associated heat sink. The model estimates the die temperature of the component as if there were no cooling devices present in the system such as a forced air cooling fan by integrating the thermal energy added when the component is active and by integrating the thermal energy removed when it is idle. A programmable power value may be used to represent the heat added to the model at each model sample period. The effect of a heat sink in cooling the idle component may be modeled by reducing the value of the heat accumulator by a predetermined fractional amount during each sample period. The decay time constant for the model may be changed by then adjusting the sample period.

Abstract: In a computer implemented method, a list of variable size integers is encoded in a memory. Each variable size integer is expressed as a set of a minimum number of bytes. A fixed number the bytes of the sets are grouped with an associated bit map into a logical memory word unit. Each bit map has one continuation bit for each of the fixed number of bytes. Each continuation bit indicating whether or not a particular variable size integer continues into a following byte. An entry is stored in an array for each possible pattern of continuation bits of the bit maps. Each entry including a plurality of fields. There is one field for each of the fixed number of bytes in each group. Each field stories a length of a corresponding set of bytes expressing a particular variable size integer in the group. The entries provide a decoding table that is indexable by the bit maps to recover the list of variable size integers.

Abstract: A portable computer and docking station combination, comprising first and second batteries and first and second battery charging circuit portions, with automatic sequencing of charging between the batteries. The system includes means for charging a first battery based on an amount of current flowing into the computer circuitry, and means for charging a second battery based on an amount of current flowing into the first battery and into the computer circuitry.

Abstract: A singulated die test socket is presented. The socket allows for die to be fully functional tested and thermal tested before packaging. The socket is created from similar silicon material as the die being tested thereby producing a match of thermal coefficients of expansion between the socket and the die. It is also possible to provide additional circuitry in the socket to aid in the testing of the die. The test socket may also be used as an integrated circuit package by adding a lid, used to seal the die within the package cavity. In both uses the socket cavity may be created with sloping sidewalls, the sloping sidewalls providing for self alignment of the die within socket cavity.

Abstract: A computer system is directed to convert a program written as a plurality of high level source code modules into corresponding machine executable code. The source code modules are compiled into an object code module, and the object code modules are translated into a single linked code module in the form of a register translation language and logical symbol table compatible with a plurality of computer system hardware architectures. The source code program structures are recovered from the linked code module, and the linked code module is partitioned into a plurality of procedure, and instructions of each of the procedures grouped into basic blocks. A procedure flow graph is constructed for each of the procedures, and a program call graph is constructed for the linked code module. The linked code module is modified by eliminating dead code and moving loop-invariant code from loops.

Abstract: An apparatus is provided for sampling instructions in a processor pipeline of a system. The pipeline has a plurality of processing stages. The apparatus includes a fetch unit for fetching instructions into a first stage of the pipeline. Certain randomly selected instructions are identified, and state information of the system is sampled while a particular selected instruction is in any stage of the pipeline. Software is informed when the particular selected instruction leaves the pipeline so that the software can read any of the sampled state information.

Abstract: A computer system for executing a binary image conversion system which converts instructions from a instruction set of a first, non native computer system to a second, different, native computer system, includes an run-time system which in response to a non-native image of an application program written for a non-native instruction set provides an native instruction or a native instruction routine. The run-time system collects profile data in response to execution of the native instructions to determine execution characteristics of the non-native instruction. Thereafter, the non-native instructions and the profile statistics are fed to a binary translator operating in a background mode and which is responsive to the profile data generated by the run-time system to form a translated native image. The run-time system and the binary translator are under the control of a server process.

Abstract: A low static enclosure has an interior for holding an electronic device therein. The electronic device has opposing walls each having a guide rail thereon. The enclosure has a bottom, a top, and a backplane between the bottom and top at their respective back edges. The backplane has an electric connector on its interior surface. The bottom and top each have a flat continuous interior facing surface with a groove extending from the front edge to the back edge. The grooves on the bottom and top are for cooperation with the guide rails on the opposing walls of the electronic device to slide the electronic device along the bottom and top respectively so that an electric connector on the electronic device mates with the electric connector on the interior surface of the backplane. The flat continuous interior facing surfaces of the bottom and top discourage ESD between the surfaces and the electronic device.

Abstract: A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream.

Abstract: An apparatus and method a method for performing two-pass real time video compression is provided. Tactical decisions such as encoding and quantization values are determined in software, whereas functional execution steps are performed in hardware. By appropriately apportioning the tasks between software and hardware, the benefits of each type of processing are exploited, while minimizing both hardware complexity and data transfer requirements. One key concept that allows the compression unit to operate in real time is that the architecture and pipelining both allow for B frames to be executed out of order. By buffering B frames, two-pass motion estimation techniques can be performed to tailor bit usage to the requirements of the frame, and thereby provide a more appealing output image.

Abstract: A variable wavelength transceiver includes a first variable wavelength transmitter, capable of generating an electromagnetic wave of a first wavelength, a second detector of an electromagnetic wave of a second wavelength, and a collision detector coupled to the second detector and the variable wavelength transmitter, the collision detector determining when the energy level of the second detector exceeds a threshold value while the variable wavelength transmitter transmits the electromagnetic wave.

Abstract: A method and apparatus for reclaiming a page of physical memory in a computer system for subsequent mappings to a virtual address is provided in a system wherein the physical memory is apportioned into a number of pages. The computer system includes a temporary storage device, such as a cache, for storing a subset of the pages in memory. Each of the pages stored in the cache are accessed using a cache page address. Virtual addresses are mapped to physical addresses responsive to monitoring use of the cache page addresses associated with the allocated physical addresses. According to the present invention, a page of physical memory is reclaimed such that a substantially even distribution of cache page addresses is maintained in physical addresses of both mapped and available pages of memory. Pages are originally placed on the clean list in response to characteristics of each page including the cache page address of the page.

Abstract: A method of operating a multiprocessor system having a predefined number of processing units for processing data, includes obtaining load information representing a loading of each of a number of randomly selected ones of the processing units. The number of randomly selected processing units is greater than 1 and substantially less than the predefined number of processing units. A least loaded of the randomly selected processing units is identified from the obtained load information. The data is directed to the identified least loaded randomly selected processing unit for processing.

Abstract: A new method of fabricating a new vertical bipolar transistor in a protection circuit is disclosed. In the disclosed system, a layer of gate electrode material is formed over a selected surface of a silicon wafer. The gate electrode material is patterned to form gates between an emitter stripe and a base contact within the bipolar transistor. In an example embodiment, the gate as well as the emitter stripe are coupled with an input source such that excess voltage is limited and excess current sunk during ESD events on the input source. A conductive channel under the gate is formed in the presence of an ESD event on the input source. The channel conductance may further be enhanced by introduction of an appropriate dopant material. Sidewall spacers may be formed adjacent to the base/emitter isolation regions. Where the bipolar transistor is a PNP transistor, a light dosage of an n-type dopant may be implanted into the base contact prior to forming the sidewall spacers.

Abstract: A local client computer includes a local hypertext server, a local application program, and a downloader for downloading a copy of a remote network document (local copy), that is accessible by the local application program, onto the client computer. When connected to the network, a downloader is executed to create the local copy on the client. When disconnected, the local copy may be accessed and modified through the client browser in a manner that is similar to when the client is connected to the network.

Abstract: A SCSI bus extender apparatus coupling a primary SCSI bus to a secondary SCSI bus includes a mechanism for detecting and resolving contention between a substantially simultaneous SELECTION operation on the primary bus and a RESELECTION operation on the secondary bus. The inventive method contemplates the bus extender arbitrating for control of the primary bus after a conflict is detected, and releasing control of the secondary bus if control of the primary bus is obtained. A target device on the secondary bus can then rearbitrate for control of the secondary bus. Once the target device controls the secondary bus, it can direct a RESELECTION signal to the bus extender, which responsively directs the signal to an initiator device on the primary bus. If the bus extender is unable to gain control of the primary bus after a conflict is detected, the SELECTION operation is allowed to proceed and the target device reattempts to assert the RESELECTION operation thereafter.

Abstract: A computer system includes a plurality of processor modules coupled to a system bus with each of said processor modules including a processor interfaced to the system bus. The processor module has a backup cache memory and tag store. An index bus is coupled between the processor and the backup cache and backup cache tag store with said bus carrying only an index portion of a memory address to said backup cache and said tag store. A duplicate tag store is coupled to an interface with the duplicate tag memory including means for storing duplicate tag addresses and duplicate tag valid, shared and dirty bits. The duplicate tag store and the separate index bus provide higher performance from the processor by minimizing external interrupts to the processor to check on cache status and also allows other processors access to the processor's duplicate tag while the processor is processing other transactions.

Abstract: A circuit for limiting voltage transient excursions on a power supply node is disclosed. The circuit includes a first field effect transistor dispose to provide a capacitance and having source and drain electrodes coupled to said external supply node path and having a gate electrode and first and second clamp transistors. A resistance is coupled between the gate electrode of said first transistor and the internal supply return node and to gate electrodes of the clamp transistors. The circuit also include process resistances between internal and external supply connection to provide a charge transfer path between external and internal supply nodes and external and internal return nodes.

Abstract: A method and an apparatus analyze a computer program for dependencies of the program output on the program input. To analyze the program, the program is transformed by a function into a Boolean expression called a verification condition. An example of this function is the weakest liberal precondition. The verification condition characterizes a condition between the input and the output of the program that must be satisfied for the output to be independent of the input. A theorem prover evaluates the verification condition to determine whether the output would depend on the input if the program was executed. If the verification condition evaluates to true, then the output is independent of the input; false, then the output depends on the input.