Abstract: In accordance with the present invention a circuit for performing an iterative process on a data stream is provided. The iterative process includes pipeline stages which operate on a portion of the data stream to produce an output which is an input to a succeeding stage. At least one of the pipeline stages includes a means for recirculating an output from the pipeline stage as an input to the pipeline stage for a predetermined number of times before passing the output to a succeeding stage. The predetermined number of times represents a clock period that includes more than one assertion of a clock signal. With such an arrangement, a circuit which performs a process, such as multiplication and division, in accordance with a particular bandwidth requirement requires less hardware than in other circuits performing the same process.

Abstract: A technique for providing a computer generated face having coordinated eye and head movement is realized by providing a computer generated movable head and at least one computer generated movable eye. The movement of the computer generated movable head and the movement of the at least one computer generated movable eye are coordinated such that the movement of the computer generated movable head follows the movement of the at least one computer generated movable eye.

Abstract: A multi-node computer network includes a plurality of nodes coupled together via a data link. Each of the nodes includes a local memory, which further comprises a shared memory. Certain items of data that are to be shared by the nodes are stored in the shared portion of memory. Associated with each of the shared data items is a data structure. When a node sharing data with other nodes in the system seeks to modify the data, it transmits the modifications over the data link to the other nodes in the network. Each update is received in order by each node in the cluster. As part of the last transmission by the modifying node, an acknowledgement request is sent to the receiving nodes in the cluster. Each node that receives the acknowledgment request returns an acknowledgement to the sending node. The returned acknowledgement is written to the data structure associated with the shared data item.

Abstract: A cache memory system includes multiple cache levels arranged in a hierarchical fashion. A data item stored in a higher level cache level is also stored in all lower level caches. The most recent version of a data item is detected during an initial lookup of a higher level cache. The initial lookup of a higher level cache includes a comparison of address bits for the next lower level cache. Thus the most recent version of a data item is able to be detected without additional lookups to the lower level cache.

Abstract: A system for indexing information includes a memory and processor. The memory stores an index to information. The processor receives a first signal representing a query for a phrase corresponding to a concatenation of adjacent portions of the information. The processor processes the first signal so as to generate a second signal representing an entry for the phrase to be stored as part of the index in the memory.

Abstract: A conservative algorithm for pruning data paths during logic circuit timing verification is disclosed. It uses the correlation between delays on data paths and clock paths in order to prune non-critical data paths during the traversal of the network. Subnetworks are identified in the larger network. Pruning data consisting of the minimum possible delay across all possible paths through the subnetwork, the deskewing clocks, the clock arrival times, and hold times at the synchronizers in the subnetwork are identified the first time each subnetwork is analyzed. In later analysis, the pruning data stored for each subnetwork is used to determine whether a data path can be pruned. A path can be pruned if it is shown to be race-free based on the pruning data. In this way, non-critical paths need only be traced once during timing verification.

Abstract: In a computerized method, a three-dimensional model is extracted from a sequence of images that includes a reference image. Each image in the sequence is registered with the reference image to determine image features. The image features are used to recover structure and motion parameters using geometric constraints in the form of a wireframe mode. A predicted appearance is generated for each image using the recovered structure and motion parameters, and each predicted appearance is registered with the corresponding image. The recovering, generating, and registering steps are repeated until the average pixel value difference (color or intensity) between the predicted appearances and the corresponding images is less than a predetermined threshold.

Abstract: A technique for acknowledging multiple objects using a computer generated face is realized by determining the location of at least two objects relative to a display device. A computer generated face is produced on the display device, wherein the computer generated face has at least one eye. The at least one eye is alternately directed between the at least two objects.

Abstract: A fault notification system detects the non-operational state of the computer, or other type of network device, and transmits network messages from the device to a monitoring system or control console in the case of a detected non-operational state. The network messages are constructed by the network device when it is operational, preferably by the operating system before any problem is detected. This message is then stored in some non-volatile storage medium, such as the BIOS memory in one embodiment. As a result, very limited operating system functionality must be replicated in the device BIOS. Only the actual transmitted message must be stored and the commands necessary to have the message sent. In some embodiments, an auxiliary processor is used to detect improper operation, preferably via a dedicated, secondary bus. It loads the relevant messages into the transport buffer for transmission to the monitoring system even where the computer's CPU may not be operational.

Abstract: A method for bit-depth increasing digital data represented by a first number of original bits which are sequentially ordered beginning with a start bit and ending with an end bit. To bit-depth increase the data, in an expanded presentation, the original bits are replicated in the sequential order starting with the start bit to form replication bits. The original bits are appended with a second number of the replication bits to form the expanded presentation of the digital data. The appended replication bits start with the start bit and are in the sequential order of the original bits.

Abstract: In order to provide a thermal coupling between a heat source and a heat sink, an integrated interleaved-fin connector is provided. A first substrate includes a first side surface and a second side surface. A plurality of heat generating devices are formed in the first side surface. A plurality of first channels are etched in the second side surface to form a plurality of first fins. A second substrate has a plurality of second channels etched therein to form a plurality of second fins and a base. The base is for thermally engaging with a heat sink. The first and second fins providing a thermally conductive path from the heat generating devices to the heat sink when interleaved with each other.

Abstract: A new class of general purpose computers called Programmable Reduced Instruction Set Computers (PRISC) use RISC techniques a basis for operation. In addition to the conventional RISC instructions, PRISC computers provide hardware programmable resources which can be configured optimally for a given user application. A given user application is compiled using a PRISC compiler which recognizes and evaluates complex instructions into a Boolean expression which is assigned an identifier and stored in conventional memory. The recognition of instructions which may be programmed in hardware is achieved through a combination of bit width analysis and instruction optimization. During execution of the user application on the PRISC computer, the stored expressions are loaded as needed into a programmable functional unit. Once loaded, the expressions are executed during a single instruction cycle.

Abstract: A method for mapping a digitized image of a face on to a reference wireframe topology in a computer system is provided, the image composed of pixels, the wireframe composed of interconnected nodes, the method including the steps of determining facial features from the pixels, determining facial landmark points from the facial features, computing displacements for each one of the interconnected nodes, and manually finetuning the displacements in response to the step of computing.

Abstract: A table of web pages is maintained by requesting a web page, receiving the requested web page, and identifying an address, such as a URL, of the received web page. A locator, such as a fingerprint, which represents the address of the received web page is entered into the table of web pages to maintain the table. The locator has a size smaller than the address.

Abstract: A method for generating synthetic speech uses detection of natural timing boundaries in words to be spoken by the synthetic speech system, to produce natural timing intervals. Phonemes are identified in the natural timing intervals. Time durations are assigned for each of the phonemes. A time duration of a selected phoneme is changed to achieve a desired time duration for a selected natural timing interval containing the phoneme. The natural timing interval may be selected to be a syllable. The natural timing interval may be selected to be the interval between two stressed phonemes. The natural timing intervals may be set to substantially the same duration between timing boundaries by changing the phoneme durations in accordance with rhythm of the language of synthesized speech. Durations of preselected phonemes, however, may remain unchanged.

Abstract: A semiconductor structure having: semiconductor devices formed in an inner region of a semiconductor chip; a seal ring formed in the chip and disposed about the inner region; and, a plurality of trenches formed along a surface of the chip. The trenches are disposed in a corner region of the chip. A portion of the seal ring is disposed between the trenches and the inner region of the chip. The trenches are disposed along axes oblique to outer edges of the chip. A method is provided for encapsulating a semiconductor chip. The method includes the steps of: providing a semiconductor chip having active semiconductor devices in an inner region of the semiconductor chip and a seal ring in the chip about the inner region; and, forming a plurality of trenches in the chip, a portion of the seal ring being formed between the trenches and the inner region of the chip. A cover is formed having bottom portions in the trenches and on the passivation layer.

Abstract: In a computerized method for labeling data records, data records are received in an index server. The records are parsed into words, and the words are stored in a full-text index. Labels are added to the data records and the full-text index. The data records are accessed by searching the full-text index using queries including the words and the labels of the data records. Labels can be removed from the full-text index.

Abstract: A variable precedence priority encoder apparatus is provided having a plurality of inputs, each receiving a corresponding bit of an input vector, and a like plurality of outputs. Each output is associated with a corresponding one of the plurality of inputs, thereby forming a plurality of input/output pairs. The encoder circuit also includes a priority assignment circuit coupling each input of the plurality of inputs to its associated corresponding output of the plurality of outputs. The priority assignment circuit assigns a priority to each input/output pair, such that an output, which corresponds to an input which receives an asserted bit, and which has a highest priority, provides an asserted bit while all other outputs provide bits that are not asserted. The priority assigned to each input can be dynamically updated within the priority assignment circuit. Updates of priority that shift the priority position by one or more inputs can be done all using the same circuit.

Abstract: A delay circuit comprises a tapped delay element line constructed from delay elements with fixed delay intervals and a multiplexer for selecting the signal at one of the taps to produce a variable delay through the circuit. The multiplexer is controlled by a selection circuit which receives an input indicative of the actual delay time through the delay circuit from an oscillator constructed from the same fixed delay elements as the delay line.

Abstract: A method and apparatus for dynamically updating virtual to physical address mappings in order to reduce cache thrashing is disclosed in an example computer system having a memory apportioned into a number of pages. A cache is included in the computer system to store a subset of the pages of memory. Each of the pages of memory is addressed by a physical address that includes a cache page address portion. The pages of cache memory are accessed using a cache page address, which corresponds to the cache page address portion of the physical address of a corresponding page of memory. The disclosed system monitors the activity of virtual addresses and uses the activity of virtual addresses to increment cache page address activity counters. The cache page address activity counters are monitored to identify those cache page addresses that are frequently being accessed within a process to identify potential performance problems, such as thrashing.