Abstract: Disclosed are a CMOS image sensor and a manufacturing method thereof. The present CMOS image sensor comprises: first, second, and third photo diodes and a plurality of transistors spaced at a predetermined distance in a semiconductor substrate; a diffusion blocking layer on substantially an entire surface of the substrate, including an opening therein exposing at least one of the photo diodes; an interlevel dielectric layer over the entire surface of the substrate, covering the diffusion blocking layer; first, second and third color filter layers over the interlevel dielectric layer, respectively corresponding to the first, second and third photo diodes, and a plurality of microlenses over the color filter layers, corresponding to each color filter layer.

Abstract: The present invention provides a method of forming metal lines in a semiconductor device having advantages of preventing an “explosion” phenomenon during a dual damascene process so as to improve the yield of the device. An exemplary embodiment of the present invention includes removing etching residues by wet cleaning the semiconductor substrate after forming the via hole, dry cleaning the semiconductor substrate after the wet cleaning, and forming a second metal line that is electrically connected with the first metal line through the via hole.

Abstract: A high quality electron microscopy sample suitable for electron holography is prepared by forming markers filled with TEOS oxide and by repeatedly applying multiple coats of an adhesive followed by a relatively low temperature cure after each application. The TEOS oxide marker is readily visible during the polish, has a similar polish rate as a semiconductor material, and reduces contamination during sample preparation. The repeated application of adhesives separated by relatively low temperature cures increases the adhesive strength of the adhesive material to the semiconductor material without making it too brittle. This results in an improved control and yield of the sample preparation process.

Abstract: A method for manufacturing an image sensor is provided. The method includes forming a metal pad on a pad region of a semiconductor substrate having an active region and the pad region, forming a metal pad opening by forming a passivation layer on an entire surface of the semiconductor substrate including the metal pad and selectively removing the passivation layer to expose the metal pad, forming a color filter array on the passivation layer of the active region by removing a photosensitive layer used for forming the color filter array through an ashing process using an end point detection method, and forming a microlens on the color filter layer.

Abstract: A semiconductor device including a semiconductor substrate having first and second device regions. A first trench is formed in the first region and a second trench is formed in the second region. The first trench and the second trench have different widths and different depths. The first trench and the second trench define device isolation regions and active regions.

Abstract: A method of manufacturing a semiconductor device including forming a dummy gate electrode which is divided into first and second areas, selectively implanting N-type ions and P-type ions into the first and second areas of the dummy gate electrode respectively and then implanting impurity ions into a boundary region between the first area and second area of the dummy gate electrode.

Abstract: A CMOS image sensor and a method for manufacturing the same improves signal efficiency by reducing a dark signal, and includes a substrate having a first conductive type comprising an image area and a circuit area, a STI isolation layer in the substrate for electrical isolation within the circuit area, and a field oxide in the substrate for electrical isolation within the image area.

Abstract: Disclosed are an MIM (Metal-Insulator-Metal) capacitor and a method of manufacturing the same. The MIM capacitor includes: a lower metal layer and a lower metal interconnection on a substrate; a barrier metal layer on the lower metal layer; an insulating layer on the barrier metal layer; an upper metal layer on the insulating layer; an interlayer dielectric layer having a via hole on the lower metal interconnection; and a plug in the via hole.

Abstract: A library test circuit for verifying functions of a plurality of standard cell library logic cells includes a core module including a plurality of standard cell library logic cells, each logic cell having a predetermined number of input vector combinations, the core module outputting test result signals according to a standard cell library; a first switch bank for outputting a first input signal to the core module so as to select cell identifiers corresponding to respective logic cells; and a second switch bank for outputting a second input signal to the core module so as to select pattern identifiers corresponding to input vector combinations of each logic cell.

Abstract: Disclosed are: (i) a method for fabricating self-aligned contact hole in a semiconductor device, and (ii) a semiconductor device having a self-aligned contact. The method comprises the steps of: (a) forming an oxide layer covering a gate structure on a semiconductor substrate, the gate structure including a gate oxide pattern, a gate electrode pattern, a hard-mask nitride pattern, and a spacer nitride on sidewalls thereof; (b) forming a mask pattern on the oxide layer; (c) forming a contact trench by removing a portion of the oxide layer, exposed by the mask pattern, to a predetermined depth; (d) forming a buffer layer on the oxide layer, including in the contact trench; (e) etching a portion of the buffer layer at a bottom of the contact trench to expose a portion of the oxide layer; and (f) forming a contact hole by etching the exposed oxide layer using a remaining buffer layer as an etching mask.

Abstract: Disclosed are a MOS transistor having a low resistance ohmic contact characteristic and a manufacturing method thereof capable of improving a drive current of the MOS transistor. A gate oxide layer, a gate electrode, and a spacer are formed on a silicon substrate, and a silicon carbide layer is deposited thereon. A photolithography process is performed, and the silicon carbide layer is etched except for predetermined portions corresponding to source-drain regions and the gate electrode. Then, a metal layer is formed on the resulting structure after performing a source-drain ion implantation process. The metal layer is heated to form a salicide layer on the gate electrode and the source-drain diffusion regions. Then, the unreacted metal layer is removed, thereby forming the MOS transistor.

Abstract: A method for forming a plurality of metal lines in a semiconductor device including forming first insulating layer patterns on a semiconductor substrate, the first insulating patterns being spaced from each other; depositing a metal layer on and between the first insulating layer patterns; planarizing the metal layer; patterning the planarized metal layer to form the plurality of metal lines between the first insulating layer patterns; and forming a second insulating layer on and between the metal lines.

Abstract: A complementary metal-oxide semiconductor (CMOS) image sensor and a method of fabricating the same arc disclosed. In a complementary metal-oxide semiconductor (CMOS) image sensor including a photodiode receiving irradiated light and generating electric charges, a plurality of conductive circuits each formed in different layers, a plurality of interlayer dielectrics insulating the conductive circuits, and a micro-lens formed of the interlayer dielectrics and focusing the irradiated light to the photodiode, the CMOS image sensor includes a lens formed in a dome shape on any one of the interlayer dielectrics and re-focusing the light focused by the micro-lens to the photodiode.

Abstract: A flash memory device includes a source region formed in an active region of a semiconductor substrate; a recessed region formed in the active region on either side of the source region, the recessed region including a recess surface having sidewalls; floating gates formed at the sidewalls of the recess surface by interposing a tunnel insulating film; a source line formed on the source region across the active region; and control gate electrodes formed at sidewalls of the source line across a portion of the active region where the floating gates are formed. The floating gates and the control gate electrodes are formed by anisotropically etching a conformal conductive film to have a spacer structure. Cell transistor size can be reduced by forming a deposition gate structure at both sides of the source line, and short channel effects can be minimized by forming the channel between the sidewalls of a recess surface.

Abstract: A method for forming gate dielectric layers having different thicknesses is provided, The method includes forming a lower oxide layer, a nitride layer, and an upper oxide layer on a semiconductor substrate; performing a first deglaze process to the semiconductor substrate keeping the lower oxide layer, the nitride layer, and the upper oxide layer in a first region, while removing the nitride layer and the upper oxide layer in second, third, and fourth regions; forming the first gate dielectric layer having a first thickness in the second, third, and fourth regions; performing a second deglaze process to the first gate dielectric layer in the third region, thereby forming a second gate dielectric layer having a second thickness; and performing a third deglaze process on the first gate dielectric layer on the fourth region, thereby forming a third gate dielectric layer having a third thickness.

Abstract: Disclosed is a method for forming a gate dielectric in a semiconductor device. The present method includes forming a first dielectric layer on a semiconductor substrate; removing a portion of the first dielectric layer to expose a portion of the substrate; forming a nitride layer on the exposed portion of the substrate and the first dielectric layer; forming a transition metal layer on the nitride layer; and oxidizing the transition metal layer to form a transition metal oxide layer.

Abstract: Methods of fabricating semiconductor devices are disclosed. An illustrated example method protects spacers and active areas by performing impurity ion implantation on an oxide layer prior to etching the oxide layer. The illustrated method includes forming a gate on a semiconductor substrate, forming a spacer on a sidewall of the gate, forming an oxide layer over the substrate, forming a mask on the oxide layer to cover a non-salicide area, implanting impurity ions into a portion of the oxide layer which is not covered by the mask, removing the portion of the oxide layer which is implanted with impurity ions, performing salicidation on the substrate, and removing the mask.

Abstract: Provided is a CMOS image sensor and method for manufacturing the same. The CMOS image sensor includes a semiconductor substrate, a gate electrode formed on the semiconductor substrate, a conductive diffusion region formed in a photodiode area of the semiconductor substrate, a floating diffusion region formed in a transistor region of the semiconductor substrate, and an oxide region formed in the semiconductor substrate below the floating diffusion region.

Abstract: A system and a method for qualifying a logic cell library storing process parameters and properties of a specific semiconductor FAB when the logic cell library is newly developed or modified is provided.

Abstract: An improved bipolar junction transistor and a method for manufacturing the same are provided. The bipolar junction transistor includes: a buried layer and a high concentration N-type collector region in a P-type semiconductor substrate; a low concentration P-type base region in the semiconductor substrate above the buried layer; a first high concentration P-type base region along an edge of the low concentration P-type base region; a second high concentration P-type base region at a center of the low concentration P-type base region; a high concentration N-type emitter region between the first and second high concentration base regions; and insulating layer spacers between the high concentration base regions and the high concentration emitter regions. In the bipolar junction transistor, the emitter-base distance can be reduced using a trench and an insulating layer spacer. This may improve base voltage and high-speed response characteristics.