Abstract: A semiconductor memory device is provided including: a spacer shaped floating gate formed on a semiconductor substrate; a dielectric layer spacer formed at one side wall of the floating gate; a third oxide layer formed over the floating gate and the dielectric layer; and a control gate formed over the third oxide layer. According to an embodiment, the structure of the floating gate in a plate shape whose center is concave is improved to the spacer structure, making it possible to minimize the size of the semiconductor memory device and to improve density. Moreover, a LOCOS process can be excluded while forming the floating gate, making it possible to more efficiently fabricate the device.

Abstract: Provided are an image sensor and a method for manufacturing the same. The image sensor comprises: a readout circuitry, an interconnection, a contact plug, and an image sensing device. The readout circuitry is formed in a first substrate. The interconnection is electrically connected to the readout circuitry over the first substrate. The contact plug is formed over the interconnection, and includes an insulating layer at regions in an upper side thereof. The image sensing device is formed over the contact plug.

Abstract: An image sensor is provided. The image sensor comprises a readout circuitry, a first image sensing device, an interconnection, and a second image sensing device. The readout circuitry is disposed in a first substrate. The first image sensing device is disposed at one side of the readout circuitry of the first substrate. The interconnection is disposed over the first substrate and electrically connected to the readout circuitry. The second image sensing device is disposed over the interconnection.

Abstract: A semiconductor device includes a semiconductor substrate in which a first trench is formed and a second trench is formed at the middle portions of the first trench; and a first ion implantation layer that is formed on the surface of the semiconductor substrate and on the bottom of the first trench, the portions formed on the bottom of the first trench being spaced from each other by the second trench. A gate is formed from the bottom of the both side walls of the first trench to the middle portions thereof; a drift region is formed at both side walls of the first trench over the second trench; and a second ion implantation layer formed on the inner surface of the second trench.

Abstract: A semiconductor device includes a semiconductor substrate including a CMOS region and a bipolar region, a first N well and a first P well in the CMOS region, a PMOS device in the first N well and an NMOS device in the first P well, a deep P well in the bipolar region, a second N well in the deep P, a second isolation layer between the deep P well and the second N well, a third isolation in the second N well, a collector in the second N well between the second and third isolation layers, and a base formed in the second N well and having a bottom surface including first type impurities to contact the emitter.

Abstract: A semiconductor device includes an isolation layer formed on and/or over a semiconductor substrate to define an isolation layer, a drift area formed in an active area separated by the isolation layer, a pad nitride layer pattern formed in a form of a plate on the drift area, and a gate electrode having step difference between lateral sides thereof due to the pad nitride layer pattern.

Abstract: Disclosed are an image sensor and a method for manufacturing the same. The image sensor includes readout circuitry and an inter-layer dielectric layer on a first substrate, a metal line in the inter-layer dielectric layer and electrically connected with the readout circuitry, a plurality of contact plugs on the metal line, and an image sensing device on the contact plugs. The image sensing device is electrically connected to the metal line through the plurality of contact plugs. The method for manufacturing an image sensor includes forming a readout circuitry on a first substrate, forming an inter-layer dielectric layer on the first substrate, forming a metal line in the inter-layer dielectric layer such that the metal line is electrically connected with the readout circuitry, forming a plurality of contact plugs on the metal line per unit pixel, and forming an image sensing device on the plurality of contact plugs.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed. The semiconductor device includes a substrate having a first conductor-type, a buried layer of a second conductor-type on the substrate, a drain, and a first guard-ring on one side of the drain, a second guard-ring on one side of the first guard-ring, and a third guard-ring on one side of the second guard-ring.

Abstract: An image sensor and a method for manufacturing an image sensor. An image sensor may include a readout circuitry which may be formed on and/or over a first substrate. An image sensor may include an interlayer dielectric layer formed on and/or over a first substrate. An image sensor may include a metal line formed on and/or over an interlayer dielectric layer, and may include a top plug. An image sensor may include an image sensing device formed on and/or over a top plug. An image sensor may include a first conductive type ion implantation area formed on and/or over an area of an image sensing device corresponding to a top plug. Methods of manufacturing an image sensor are disclosed.

Abstract: Provided are an image sensor and a method for manufacturing the same. According to an embodiment, a semiconductor substrate is provided comprising a readout circuit. An interconnection electrically connected to the readout circuit and an interlayer dielectric are disposed over the semiconductor substrate. An image sensing unit is disposed over the interlayer dielectric and comprises a first doping layer and a second doping layer stacked therein. A first via hole is formed, exposing the interconnection through the image sensing unit. A fourth metal contact is formed in the first via hole to electrically connect the interconnection and the first doping layer. A fifth metal contact is formed over the fourth metal contact, the fifth metal contact being electrically insulated from the fourth metal contact and electrically connected to the second doping layer.

Abstract: Disclosed are a dual bit type NROM flash memory device and a method for manufacturing the same using a self-aligned scheme. The flash memory device includes a plurality of bit lines buried in a substrate in one direction while being spaced apart from each other at a regular interval; floating gates aligned at both sides of each of the bit lines on the substrate; and a plurality of word lines spaced apart from each other at a regular interval while crossing the bit lines. In the flash memory device of an embodiment, polysilicon is used for a trapping layer, so the programming and erasing operations can be performed at a higher speed, a threshold voltage (Vt) window is widened, and retention characteristics are improved.

Abstract: Provided are an image sensor and a method for manufacturing the same. The image sensor comprises a readout circuitry, an interconnection, an image sensing device, a first conductive-type ion implantation layer, and a via plug. The readout circuitry is formed in a first substrate. The interconnection is formed over the first substrate. The interconnection is electrically connected to the readout circuitry. Then image sensing device is formed over the interconnection. The image sensing device comprises a first conductive-type conductive layer and a second conductive-type conductive layer. The first conductive-type ion implantation layer is formed in a portion of the second conductive-type conductive layer of the image sensing device. The via plug penetrates through the first conductive-type ion implantation layer and the first conductive-type conductive layer to electrically connect the first conductive-type conductive layer to the interconnection.

Abstract: A method for manufacturing an image sensor including forming a microlens array over a color filter array, forming a capping layer over the semiconductor substrate including the microlens array, forming a pad mask over the capping layer, and then exposing a pad in an interlayer dielectric layer.

Abstract: A voltage regulator uses a comparing apparatus having hysteresis characteristics. The voltage regulator includes a comparator for comparing a comparison voltage with a reference voltage, and outputs a result of the comparison; a switching controller for generating a plurality of switching signals in response to the comparison result; resistors connected in the form of a string, to divide the comparison voltage into a plurality of voltages; and a switching box for selecting one of the plural voltages, as the comparison voltage, in response to the switching signals.

Abstract: Provided are a nonvolatile memory device, a method of manufacturing the nonvolatile memory device, and a method of manufacturing a flat panel display device provided therein with the nonvolatile memory device. According to an embodiment, an amorphous silicon layer is formed on a substrate, and then annealed by using an Excimer laser to form a crystallized silicon layer. A nitrogen plasma treatment is performed for the crystallized silicon layer to planarize an upper surface of the crystallized silicon layer. An ONO layer is formed on the nitrogen plasma-treated crystallized silicon layer. A metal layer is formed on the ONO layer. The metal layer, the ONO layer and the nitrogen plasma-treated crystallized silicon layer are patterned.

Abstract: A flash memory device and a method of manufacturing a flash memory device. A flash memory device may include an isolation layer and/or an active area over a semiconductor substrate, a memory gate formed over an active area, a control gate formed over a semiconductor substrate including a memory gate, and/or a common source line contact formed over a semiconductor substrate including a control gate. A flash memory device may include a source plate having substantially the same interval as an interval of an active area of a bit line. A source plate may include an active area in which a common source line contact may be formed. A common source line contact may include a long butting contact extending in a direction traversing an active area.

Abstract: A non-volatile memory device and a driving method thereof. The non-volatile memory device includes a floating gate formed on and/or over a first type well, and transistors formed on and/or over a second type well and connected in series to the floating gate. One of the transistors is a first transistor for program and erase operations, and the other one is a second transistor for a reading operation.

Abstract: A semiconductor device having a common source structure and method of manufacturing the same are provided. In one embodiment, the method includes: forming a plurality of gate lines on a semiconductor substrate, each constituted by a floating gate, a dielectric layer, and a control gate having a line form; forming a first dielectric layer on the semiconductor substrate including the gate line; forming a trench having the line form in the first dielectric layer, wherein the trench exposes the semiconductor substrate between the gate lines; and forming a common source in the trench. According to an embodiment, the common source is implemented as a poly line in the trench. Therefore, etching the substrate to provide a trench for a common source can be excluded. Accordingly, it is possible to inhibit the common source from being opened due to a remaining material in a trench, and reduce damage to the semiconductor substrate.

Abstract: A method of manufacturing a MIM capacitor of a semiconductor device and a MIM capacitor. A MIM structure and a metal layer may be formed using a single process. A method of manufacturing a MIM capacitor may include forming a hole on and/or over a lower metal wire region. A method of manufacturing a MIM capacitor may include forming a lower metal layer, an inter-metal dielectric and/or an upper metal layer on and/or over a hole to form a MIM structure. Patterns to form a MIM structure and a metal layer may be formed at substantially the same time. If etching is performed with a photoresist pattern as a mask, a MIM structure and a metal layer structure may be formed at substantially the same time using a single mask.

Abstract: An apparatus for transferring serial data (e.g., a serial interface using a single wire) generally includes a detector configured to detect a first level time period and a second level time period of an input signal, and a computing unit configured to compute a duty or duty cycle of the input signal and generate an output signal based on the duty or duty cycle.