Abstract: A semiconductor device and a method of fabricating the semiconductor device is provided. In the method, a semiconductor substrate defining a device region and an outer region at a periphery of the device region is provided, an align trench is formed in the outer region, a dummy trench is formed in the device region, an epi layer is formed over a top surface of the semiconductor substrate and within the dummy trench, a current path changing part is formed over the epi layer, and a gate electrode is formed over the current path changing part. When the epi layer is formed, a current path changing trench corresponding to the dummy trench is formed over the epi layer, and the current path changing part is formed within the current path changing trench.

Abstract: A semiconductor memory device and a method of manufacturing the same.

Abstract: A real-time image generator is disclosed. A real-time image generator may include a first block extracting only a luminance component having a saturation, hue, and value domain from red, green and blue values of an image. A second block outputs a log summation value and pixel count value with respect to a luminance component of an overall image by using the extracted luminance component and a natural log value. A third block calculates a luminance average value of the image by using the natural log summation value and the pixel count value outputted in the second block, the third block generating a tone mapping look up table including a tone mapping operator (Ld) for each luminance range to obtain a final output image using the calculated luminance average value. The third block outputs a tone mapped red, green and blue value by multiplying a corresponding tone mapping operator (Ld) of the tone mapping look up table by a red, green and blue value of the input image.

Abstract: A noise filter according to an embodiment includes: a first filter that functions as an edge detector to detect a high-frequency component area of an image; a second filter that performs a noise filtering function for the remaining areas of the image while conserving the high-frequency component area detected by the first filter; and a function processor that controls operations of the first filter and the second filter. According to an embodiment, since noise filtering for only a noise component area is performed by dividing the image into a high-frequency component area and a noise component area, it is possible to minimize deterioration of the high-frequency area and improve the resolution and quality of the image.

Abstract: A symmetrical signal generator that includes a first signal part configured to produce a first output pulse signal using a first input pulse signal and a second input pulse signal asymmetrical to each other, and a second signal part configured to produce a second output pulse signal using the first input pulse signal and the second input pulse signal. The second output pulse signal is one inverted to be symmetrical to the first output pulse signal.

Abstract: Disclosed is an LCD driver IC including: a POR (Power On Reset) circuit; and a counter, which receives a signal from the POR circuit to delay time and releases a RESETB of the POR circuit after power of a gate driver IC is stabilized.

Abstract: A semiconductor memory device, a method of manufacturing the same, and a cell array of a semiconductor memory device are provided. The semiconductor memory device includes: a first gate insulation layer and a second gate insulation layer, being spaced a predetermined distance from each other, on a portion of a semiconductor substrate; a select gate on the first gate insulation layer; a floating gate on the second gate insulation layer; a third gate insulation layer on the floating gate; a control gate on the third gate insulation layer; a first ion implantation region in the semiconductor substrate between the select gate and the floating gate; a second ion implantation region in the semiconductor substrate at a side of the select gate opposite the first ion implantation region; and a third ion implantation region in the semiconductor substrate at a side of the floating gate opposite the first ion implantation region.

Abstract: A temperature independent type reference current generating device and methods thereof. A temperature independent type reference current generating device may include a first reference current generator generating a first reference current having a first element decreasing according to a temperature, a second reference current generator generating a second reference current having a second element increasing according to the temperature, and/or mirroring and outputting a second reference current and/or a mirrored second reference current. A temperature independent type reference current generating device may include a first current mirror mirroring a first reference current and/or outputting a mirrored first reference current, and a second current mirror adding a mirrored first reference current and a mirrored second reference current, and/or mirroring a result of an addition to output a mirrored result as an output reference current.

Abstract: Disclosed are a semiconductor device and a manufacturing method thereof. The semiconductor device can include a recess formed in an active area of a semiconductor substrate, an insulating layer formed in the recess, a source electrode and a drain electrode spaced apart from the source electrode on the insulating layer, a carbon nanotube layer formed between the source and drain electrodes, an oxide layer pattern covering at least the carbon nanotube layer, and a gate electrode formed on the oxide layer pattern.

Abstract: An LDMOS device includes a second conduction type buried layer, a first conduction type drain extension region configured to be formed on and/or over a region of the second conduction type buried layer, a second conduction type drain extension region configured to be formed in a partial region of the first conduction type drain extension region, a first conduction type body, a first guard ring configured to be formed around the second conduction type drain extension region and configured to include a second conduction type impurity layer, and a second guard ring configured to be formed around the first guard ring and configured to include a high-voltage second conduction type well and a second conduction type impurity layer. Further, the second conduction type impurity layer of the first guard ring and the second conduction type impurity layer of the second guard ring operate as an isolation.

Abstract: A semiconductor device includes a laterally double diffused metal oxide semiconductor (LDMOS) transistor formed on a partial region of a epitaxial layer of a first conductive type, a bipolar transistor formed on another partial region of the epitaxial layer of the first conductive type, and a guard ring formed between the partial region and the another partial region. The guard ring serves to restrain electrons generated by a forward bias operation of the LDMOS transistor from being introduced into the bipolar transistor.

Abstract: A high-voltage transistor may include a semiconductor substrate, and a gate electrode formed on and/or over the semiconductor substrate. Further, the high-voltage transistor may include source/drain regions formed on and/or over the semiconductor substrate at one side of the gate electrode, and impurity layers having a super junction structure and formed on and/or over a boundary of a drift region disposed below the gate electrode.

Abstract: An LDMOS device may include at least one of a second conduction type buried layer and a first conduction type drain extension region. An LDMOS device may include a second conduction type drain extension region configured to be formed in a portion of the first conduction type drain extension region. The second conduction type drain extension region may include a gate pattern and a drain region. An LDMOS device may include a first conduction type body having surface contact with the second conduction type drain extension region and may include a source region. An LDMOS device may include a first guard ring formed around the second conduction type drain extension region. An LDMOS device may include a second guard ring configured to be formed around the first guard ring and configured to be connected to a different region of the second conduction type buried layer.

Abstract: Disclosed are example bipolar transistors capable of reducing the area of a collector, reducing the distance between a base and a collector, and/or reducing the number of ion implantation processes. A bipolar transistor may includes a trench formed by etching a portion of a semiconductor substrate. A first collector may be formed on the inner wall of the trench. A second collector may be formed inside the semiconductor substrate in the inner wall of the trench. A first isolation film may be formed on the sidewall of the first collector. An intrinsic base may be connected to the third collector. An extrinsic base may be formed on the intrinsic base and inside the first isolation film. A second isolation film may be formed on the inner wall of the extrinsic base. An emitter may be formed by burying a conductive material inside the second isolation film.

Abstract: A method of manufacturing a flash memory device is provided. First and second gates are formed on first and second dielectrics and spaced apart from each other on a cell area of a substrate. A third gate is formed on a third dielectric that is formed on first opposing sidewalls of the first gate and extending on a portion of the substrate from the first opposing sidewalls. A fourth gate is formed on a fourth dielectric that is formed on second opposing sidewalls of the second gate and extending on a portion of the substrate from the second opposing sidewalls. The third gate and third dielectric on one of the first opposing sidewalls facing the second gate and the fourth gate and fourth dielectric on one of the second opposing sidewalls facing the first gate are removed. Drain areas are formed at outer sides of the third and fourth gates, and a common source area is formed between the first and second gates.

Abstract: A circuit and method for driving a line repair amplifier includes a line repair amplifier which can be driven by using a single side input which can use an amplifier which drives a gray high side only and an amplifier which drives a gray low side only separately in a liquid crystal display device which uses a line repair amplifier.

Abstract: A vertical junction field-effect transistor in a CMOS base-technology. The vertical junction field-effect transistor includes a semiconductor substrate having a source region and a drain region, a main-channel region formed between the source region and the drain region, a well region formed on the main-channel region between the source region and the drain region, vertical pinch-off regions formed at both source and drain ends or only on the source-end of the well region on the main-channel region in the source region and the drain region respectively, a source contact on the vertical pinch-off region in the source region, a drain contact on the vertical pinch-off region in the drain region, a gate contact on the well region between the source contact and the drain contact and shallow trench isolations formed on the well region.

Abstract: Embodiments provide an illumination apparatus including an adapter coupled detachably and electrically to an incandescent lamp socket or a halogen lamp socket, configured to convert alternating power to driving power; and a light emitting device connected detachably and electrically to the adapter, configured to emit light according to the driving power from the adapter.

Abstract: An illumination apparatus can include an adapter that converts alternating power into driving power, and controls one or more of the color, brightness, chroma, and blinking of a light emitting device; and a light emitting device illumination part detachably and electrically connected to the adapter, containing one or more light emitting devices configured to emit light in accordance with the driving power and control.

Abstract: Disclosed are an LDMOS device and a method for manufacturing the same capable of decreasing the concentration of a drift region between a source finger tip and a drain, thereby increasing a breakdown voltage. An LDMOS device includes a gate which is formed on a substrate, a source and a drain which are separately arranged on both sides of the substrate with the gate interposed therebetween, a field oxide film which is formed to have a step between the gate and the drain, a drift region which is formed of first condition type impurity ions between the gate and the drain on the substrate, and at least one internal field ring which is formed inside the drift region and formed by selectively ion-implanting second conduction type impurity ions in accordance with the step of the field oxide film.