Abstract: An image sensor can include a gate insulation layer, a gate electrode, a photodiode, and a floating diffusion region. The gate insulation layer can be formed on and/or over a semiconductor substrate for a transfer transistor. The gate insulation layer includes a first gate insulation layer having a central opening and a second gate insulation layer formed on and/or over an uppermost surface of the first gate insulation layer including the opening. The gate electrode can be formed on and/or over the gate insulation layer. The photodiode can be formed in the semiconductor substrate at one side of the gate electrode so as to generate an optical charge. The floating diffusion region can be formed in the semiconductor at the other side of the gate electrode opposite to the photodiode. The floating diffusion region can be electrically connected to the photodiode through a channel so as to store the optical charge generated from the photodiode.

Abstract: Disclosed is an image sensor. The image sensor includes a substrate having photodiodes therein; a dielectric layer on the substrate; a passivation layer on the dielectric layer exposing the dielectric layer in a region corresponding to a first color filter; and a color filter layer on the exposed dielectric layer and the passivation layer.

Abstract: An image sensor includes readout circuitry on a first substrate, a metal line electrically connected with the readout circuitry, a dielectric on the metal line, an image sensing device on the dielectric, including first and second conductivity type layers, a contact plug in a via hole penetrating the image sensing device to connect the first conductivity type layer with the metal line, and a sidewall dielectric in the via hole at a sidewall of the second conductivity type layer.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. A method of manufacturing a semiconductor device may include forming a gate electrode over a semiconductor substrate, a second conductive type ion implantation region at opposite sides of a gate electrode, a second conductive type ion implantation region as a first conductive type second ion implantation region by implanting a first conductive type impurity over opposite sides of said gate electrode, and/or forming a first conductive type first ion implantation region that substantially surrounds a first conductive type second ion implantation region. A method of manufacturing a semiconductor device may form an N type MOSFET and/or a P type MOSFET using a single photolithography process for each N+ source/drain photolithography process and/or P+ source/drain photolithography process.

Abstract: Disclosed is a flash memory device and a method of manufacturing the same. The flash memory device includes a floating gate formed on a semiconductor substrate, a select gate self-aligned on one sidewall of the floating gate, and an ONO pattern interposed between the floating gate and the select gate. A self-aligned split gate structure is formed for an EEPROM tunnel oxide cell flash memory device employing a split gate structure, so that a cell current is constant and the erasing characteristic between cells is uniform, thereby improving the reliability.

Abstract: A backside illumination (BSI) image sensor having a light receiving part at the wafer or die backside, and a manufacturing method thereof, are disclosed. The method includes polishing the light receiving part so that a super via protrudes, forming a first insulating layer to cover the protruding super via and the light receiving part, forming a photoresist pattern on the first insulating layer to expose a pad region, etching the first insulating layer to form spacers at sides of the protruding super via, repeatedly forming a second insulating layer covering the spacers, the super via and the light receiving part and etching the second insulating layer so that the spacers increase in width and cover an upper surface of the light receiving part, and forming a metal pad in the pad region to contact the super via.

Abstract: Disclosed are uracil compounds represented by Formula 1, a method for preparing the compounds, and a herbicide including the same as an active ingredient: wherein R1, R2, R3, R4, R5, X, Y, Z and W are the same as defined in the detailed description.

Abstract: A semiconductor memory device and a method of fabricating the same which is suitable for fabrication of a non-volatile memory, such as an EEPROM, using a polysilicon-insulator-polysilicon (PIP) process. The semiconductor memory device includes isolation layers defining a tunneling region and a read transistor region of a semiconductor substrate, a lower polysilicon film formed on and/or over the tunneling region and the read transistor region, a dielectric film formed on and/or over the lower polysilicon film in the tunneling region, and an upper polysilicon film formed on and/or over the dielectric film.

Abstract: A back side illumination image sensor according to an embodiment includes: a photosensitive device and a readout circuit on the front side of a first substrate; an interlayer dielectric layer on the front side of the first substrate; a metal line on the interlayer dielectric layer; a pad having a step on the interlayer dielectric layer; and a second substrate bonded with the front side of the first substrate over the interlayer dielectric layer, metal line, and pad.

Abstract: Provided are a photomask, an image sensor, and a method of manufacturing the image sensor. The image sensor can include photodiode structures, color filters, a planarization layer, and microlenses. The photodiode structures can be disposed on a semiconductor substrate according to unit pixel. The color filters can be disposed on the semiconductor substrate in a matrix arrangement above the photodiode structures. The planarization layer can cover the entire semiconductor substrate and includes cavities in regions of the planarization layer corresponding to boundaries between the color filters. The cavities may be arranged at boundaries between unit pixels. The microlenses can be disposed on the planarization layer such that portions of the microlenses are arranged in the cavities of the planarization layer.

Abstract: An image sensor has a large bridge margin from a repulsive force between adjacent micro lenses having different surface properties. The image sensor has a larger bridge margin with a configuration of a stepped portion between two areas, where the first and the second group of micro lenses are formed, over a planarization layer below these two areas. Thus, a zero gap is realized, where no gap between micro lenses exists, and the fill factor of micro lens is maximized. By the realization of the zero gap, interference effects decrease, noise decreases, and fill factor increases, and thus the sensitivity of an image sensor increases, especially the green sensitivity.

Abstract: Disclosed is a method for manufacturing a back side illumination image sensor. The method includes defining a pixel area by forming a first isolation area in a first substrate; forming a photo detecting unit buried in the pixel area; forming an ion implantation layer on the photo detecting unit; growing a second substrate on the first substrate having the ion implantation layer; forming a logic unit electrically connected to the first substrate on the second substrate; forming an insulting layer and an interconnection on the second substrate; and exposing the photo detecting unit by grinding a backside of the first substrate.

Abstract: An optimized Mobile Industry Processor Interface (MIPI) includes a transmitter physical (PHY) layer configured to convert input data into serial data and transmit the serial data in synchronization with a high-speed clock, a receiver PHY layer configured to convert the serial data into 8-bit parallel data in synchronization with the clock received from the transmitter, a bit merge block configured to merge the parallel data received from the receiver PHY layer so as to form 32-bit data using multiple lanes and to transmit the 32-bit data to a receiver protocol layer, the receiver protocol layer being configured to decode and recognize the data received from the bit merge block.

Abstract: A method of fabricating a semiconductor device and a flash memory device are provided. The method of fabricating the semiconductor device includes: forming a nitride film on a semiconductor substrate; forming a sacrificial vertical structure on the nitride film; forming sacrificial spacers on lateral surfaces of the sacrificial vertical structure; performing an initial patterning of the nitride film using the sacrificial vertical structure and the sacrificial spacers as etch masks; removing the sacrificial spacers after the initial patterning of the nitride film and forming gate electrodes on the lateral surfaces of the sacrificial vertical structure; and removing the sacrificial vertical structure from between the gate electrodes and performing a secondary patterning of the nitride film using the gate electrodes as etch masks.

Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate formed therein with a first conductive type well, and an LDMOS device formed on the substrate. The LDMOS device includes a gate electrode, gate oxides formed below the gate electrode, a source region formed in the substrate at one side of the gate electrode, and a drain region formed in the substrate at an opposite side of the gate electrode. The gate oxide includes first and second gate oxides disposed side-by-side and having thicknesses different from each other.

Abstract: An electrostatic discharge protection device, a method of manufacturing the same, and a method of testing the same. The electrostatic protection device includes a plurality of device isolation regions formed in a semiconductor substrate at a predetermined width and a predetermined depth that each sequentially increase from a circuit device formation region of the semiconductor substrate to a ground region of the semiconductor substrate, a plurality of gate electrodes formed over the semiconductor substrate in spaces between adjacent ones of the device isolation regions, and a plurality of source regions and drain regions formed in the semiconductor substrate at both lateral sides of the gate electrode.

Abstract: An electrostatic discharge (ESD) protection circuit includes a substrate, and a plurality of unit bipolar transistors formed in the substrate. Each of the plurality of unit bipolar transistors may include a first-conductivity-type buried layer formed in the substrate, a first-conductivity-type well formed over the first-conductivity-type buried layer, a second-conductivity-type well formed in the first-conductivity-type well, a first-conductivity-type vertical doping layer vertically formed from the surface of the substrate to the first-conductivity-type buried layer so as to surround the first-conductivity-type well, and a first-conductivity-type doping layer and a second conductivity-type doping layer formed in the second-conductivity-type well. The first-conductivity-type doping layer of any one of the adjacent unit bipolar transistors and the first-conductivity-type vertical doping layer of another one of the adjacent unit bipolar transistors may be connected to each other.

Abstract: An image sensor includes a first substrate, readout circuitry, an electrical junction region, a metal interconnection and an image sensing device. The readout circuitry is formed on and/or over the first substrate and the electrical junction region is formed in the first substrate and electrically connected to the readout circuitry. The metal interconnection is electrically connected to the electrical junction region. The image sensing device is formed on and/or over the metal interconnection.

Abstract: Disclosed are a back side illumination image sensor and a method for manufacturing the same. The back side illumination image sensor includes an isolation region and a pixel area on a front side of a first substrate; a photo detector and a readout circuitry on the pixel area; an interlayer dielectric layer and a metal line on the front side of the first substrate; a second substrate bonded to the front side of the first substrate formed with the metal line; a pixel division ion implantation layer on the isolation region at a back side of the first substrate; and a micro-lens on the photo detector at the back side of the first substrate.

Abstract: Disclosed are an image sensor and a method for manufacturing the same. The image sensor includes an isolation trench formed in a semiconductor substrate corresponding to a logic region and a pixel separating trench formed on the semiconductor substrate corresponding to a pixel region and having a depth shallower than a depth of the isolation trench of the logic region, a barrier region formed below the pixel separating trench, a pixel separator formed inside the pixel separating trench, a gate formed above the semiconductor substrate, a first doped region formed at a deep region of the semiconductor substrate corresponding to one side of the gate, an additionally-doped region interposed between the first doped region and the barrier region, and a second doped region formed at a shallow region of the semiconductor substrate such that the second doped region makes contact with the first doped region.