Abstract: To program a first programmable gate array, for example a first FPGA, in a distributed computer system, a configuration of a first configuration logic on the first programmable gate array is provided. The first configuration logic is configured to receive a first user bitstream from a configuration software for configuring a first user logic on the first programmable gate array and to store the first user bitstream on a non-volatile memory of the first programmable gate array for the purpose of subsequently configuring a first user logic on the first programmable gate array according to the specifications from the first user bitstream. In an expansion stage of the invention, a configuration of a programming logic on the first programmable gate array is also provided for programming a second programmable gate array, which is connected to the first programmable gate array to form a daisy chain.

Abstract: A method of reducing training data via a system having an encoder, wherein at least a portion of the training data forms a temporal sequence and is combined into a first set of training data, and the encoder maps input data to prototype feature vectors of a set of prototype feature vectors. A first input datum is received from the first set of training data, and propagated by the encoder. The input datum is assigned one or more feature vectors by the encoder, and depending on the assigned feature vectors, a defined set of prototype feature vectors is determined and assigned to the first input datum. An aggregated vector is created for the first input datum. A second aggregated vector is created for the second input datum and the first and second aggregated vectors are compared and a measure of similarity for the aggregated vectors is determined.

Abstract: A heat sink with a first sub-area and a second sub-area, designed for contacting a large area of a printed circuit board populated with electronic components. A thermal isolation extends between the first sub-area and the second sub-area, and a rigid mechanical connection that spans the thermal isolation connects the first sub-area to the second sub-area. As a result, the heat sink allows an assignment of sub-areas to electronic components on the printed circuit board, and contributes to mechanical stabilization of the printed circuit board.

Abstract: A computer-implemented method for restructuring a predefined distributed real-time simulation network, wherein the simulation network has a plurality of network nodes and a plurality of data connections, wherein each network node has at least one data connection interface for connecting a data connection, wherein the network nodes are at least partially in communication via the data connections, and wherein during operation of the simulation network a simulation application is executed on at least one network node. The method permits a structure for the real-time simulation network to be automatically found in which the critical communication connections are reduced and avoided as much as possible by determining the topology of the simulation network so that topology information concerning the network nodes and the data connections between the network nodes is available by determining expected values for node data rates or node latencies for the network nodes of the simulation network.

Abstract: A module with a functional unit for generating a data stream with a data output for outputting the data stream to a serialization unit provided for receiving a data stream from a serialization unit of a first series. A serialization unit of a second series is set up to serialize the data stream and output it through the data output, and a configuration data input receives configuration data defining a first register configuration of a serialization unit. A mapping of register addresses of the serialization unit of the first series to register addresses of the serialization unit of the second series can be stored in a data memory of the module. The configuration unit is set up to read in the configuration data, to use the mapping, and to configure the registers of the serialization unit of the second series according to the configuration of the second register.

Abstract: A computer-implemented method for integrating at least one signal value into a virtual control unit. The virtual control unit is executed on a simulation platform by means of a personal computer and requires at least one input signal, wherein at least one signal value can be assigned to the input signal. A simulation function provides at least one first simulated signal value to the virtual control unit. The microcontroller abstraction layer has a software component for integrating the first simulated signal value and a second external signal value into a virtual control unit, wherein the second external signal value is provided by an external peripheral device. A user makes a selection for the input signal via a user interface as to whether the software component is to use the first simulated signal value or the second external signal value.

Abstract: A method for planning the design of partitions for a programmable gate array comprising different types of logic blocks of predetermined position, and a plurality of program routines comprising at least one first program routine and at least one further program routine. A mapping of a first partition of the programmable gate array with the first program routine and at least one further partition of the programmable gate array with the at least one further program routine is performed. The need of the first program routine for the individual types of logic blocks is determined. Meeting this need with the logic block resources of corresponding type available in the first partition. At least one logic block of corresponding type from the further partition or at least one of the further partitions into the first partition is transferred.

Abstract: A method for monitoring message packets that are exchanged between at least two control units. The message packets are concatenated in a data stream and each have an identifier, a payload, and a length specification of the payload described by a data item of predefined word size. The at least two control units are connected by a distributor. The distributor is connected by a first distributor port to a first of the at least two control units, is connected by a second distributor port to a second of the at least two control units, and is connected by a third distributor port to a computer system. The data stream flows through the first and distributor port for communication between the first node and the second node. The computer system has a memory, and information on the respective identifiers of the message packets is stored in the memory.

Abstract: A method and replay unit for sending secured messages via a messaging system to a receiver ECU to be tested, wherein the replay unit is connected to the device under test via the messaging system, wherein the replay unit is set up to receive first secured messages to be replayed, to remove from the first secured messages a first counter value and a first authenticator, and to generate a second authenticator by means of a second counter value, an encryption algorithm and a key, and wherein the replay unit is set up to generate second secured messages by adding the second counter value and the second authenticator to the first messages, and wherein the replay unit is further adapted to send the second secured messages to the recipient device under test via the messaging system.

Abstract: A method for the usage-based licensing of one or more applications in a container, wherein the container comprises a license module, an application queries the presence of an application license via the license module and is only executed if an application license is present. In the license module, a linking of one or more application licenses with a unique identifier is stored, and the container comprises a settlement module, which retrieves a usage unit from an external license source. For the duration of an obtained usage unit, the settlement module provides the unique identifier in a secure data storage so that all applications linked with the unique identifier can be executed. A computer system and a computer program product are also provided.

Abstract: A computer-implemented method for real-time simulation of the operation of a specific electric motor by a simulator arithmetic unit comprising a programmable logic device on which a generic motor model is implemented. The method includes: providing a generic system of equations corresponding to the generic motor model; receiving specific information corresponding to the specific motor to be simulated for the generic system of equations and inputting this information into the generic system of equations; generating a specific library containing at least some of the arithmetic operations required for the matrix operations for calculating the operation of the specific motor; implementing references in the generic motor model to the arithmetic operations of the specific library required for real-time simulation of the operation of the specific electric motor; and simulating the operation of the specific electric motor by running the generic motor model on the simulator arithmetic unit.

Abstract: To program a first programmable gate array, for example a first FPGA, in a distributed computer system, a configuration of a first configuration logic on the first programmable gate array is provided. The first configuration logic is configured to receive a first user bitstream from a configuration software for configuring a first user logic on the first programmable gate array and to store the first user bitstream on a non-volatile memory of the first programmable gate array for the purpose of subsequently configuring a first user logic on the first programmable gate array according to the specifications from the first user bitstream. In an expansion stage of the invention, a configuration of a programming logic on the first programmable gate array is also provided for programming a second programmable gate array, which is connected to the first programmable gate array to form a daisy chain.

Abstract: A method for planning the design of partitions for a programmable gate array comprising different types of logic blocks of predetermined position, and a plurality of program routines comprising at least one first program routine and at least one further program routine. A mapping of a first partition of the programmable gate array with the first program routine and at least one further partition of the programmable gate array with the at least one further program routine is performed. The need of the first program routine for the individual types of logic blocks is determined. Meeting this need with the logic block resources of corresponding type available in the first partition. At least one logic block of corresponding type from the further partition or at least one of the further partitions into the first partition is transferred.

Abstract: A test device for testing a distance sensor operating with ultrasonic waves, wherein the distance sensor to be tested comprises at least a sensor radiating element for emitting a transmission signal and a sensor receiving element for receiving a reflected signal. For effective and accurate testing and stimulation of the distance sensor, the test device has a test receiving element for receiving ultrasonic waves emitted from the distance sensor to be tested, and at least one test radiating element for radiating test ultrasonic waves, and a signal processing unit, wherein ultrasonic waves received by the test receiving element are transmitted as a received signal to the signal processing unit and the signal processing unit, as a function of the received signal and simulation distance information relating to a distance to be simulated, and determines an excitation signal for the test radiating element.

Abstract: A computer-implemented method for generating program code based on one or more blocks of a block diagram, at least one block including a block variable. The method comprises opening the block diagram in a model editor, retrieving generation settings for the block variable from a data definition tool, the generation settings comprising a scope of the variable, determining that a modification rule is referenced in the generation settings, and retrieving the referenced modification rule from the data definition tool, wherein a modification rule comprises a filter condition and one or more code changes. A processor generates program code based on the block diagram and the generation settings and applies the referenced modification rule to the block variable in the generated code, which includes verifying that the filter condition is fulfilled for the block variable and applying the code changes to each occurrence of the variable in the code.

Abstract: A heat sink with a first sub-area and a second sub-area, designed for contacting a large area of a printed circuit board populated with electronic components. A thermal isolation extends between the first sub-area and the second sub-area, and a rigid mechanical connection that spans the thermal isolation connects the first sub-area to the second sub-area. As a result, the heat sink allows an assignment of sub-areas to electronic components on the printed circuit board, and contributes to mechanical stabilization of the printed circuit board.

Abstract: A computer-implemented method for integrating at least one signal value into a virtual control unit. The virtual control unit is executed on a simulation platform by means of a personal computer and requires at least one input signal, wherein at least one signal value can be assigned to the input signal. A simulation function provides at least one first simulated signal value to the virtual control unit. The microcontroller abstraction layer has a software component for integrating the first simulated signal value and a second external signal value into a virtual control unit, wherein the second external signal value is provided by an external peripheral device. A user makes a selection for the input signal via a user interface as to whether the software component is to use the first simulated signal value or the second external signal value.

Abstract: A module with a functional unit for generating a data stream with a data output for outputting the data stream to a serialization unit provided for receiving a data stream from a serialization unit of a first series. A serialization unit of a second series is set up to serialize the data stream and output it through the data output, and a configuration data input receives configuration data defining a first register configuration of a serialization unit. A mapping of register addresses of the serialization unit of the first series to register addresses of the serialization unit of the second series can be stored in a data memory of the module. The configuration unit is set up to read in the configuration data, to use the mapping, and to configure the registers of the serialization unit of the second series according to the configuration of the second register.

Abstract: A method for generating a technical system model executable on a test unit, wherein the test unit and the executable model are designed for real-time-capable testing of a control unit connected to the test unit, and wherein the executable model is constructed from a plurality of executable submodels communicating with each other, wherein each executable submodel has a separate address space and/or is executed on a separate processor or separate processor core when a test of a control unit connected to the test unit is being run.

Abstract: A method for troubleshooting the program logic of a computer system. A first logic circuit and a first monitoring circuit, which is communicatively isolated from it, are programmed on a first programmable gate array of the computer system. A second logic circuit and a second monitoring circuit, which is communicatively isolated from it, are programmed on a second programmable gate array of the computer system. After an error has been detected in the program logic of the computer system, a first signal line, which applies a signal from the first logic circuit to a first signal input of the first monitoring circuit, is programmed in the first programmable gate array without changing the first logic circuit, and a second signal line, which applies a signal from the second logic circuit, is programmed in the second programmable gate array without changing the second logic circuit.