Abstract: To program a first programmable gate array, for example a first FPGA, in a distributed computer system, a configuration of a first configuration logic on the first programmable gate array is provided. The first configuration logic is configured to receive a first user bitstream from a configuration software for configuring a first user logic on the first programmable gate array and to store the first user bitstream on a non-volatile memory of the first programmable gate array for the purpose of subsequently configuring a first user logic on the first programmable gate array according to the specifications from the first user bitstream. In an expansion stage of the invention, a configuration of a programming logic on the first programmable gate array is also provided for programming a second programmable gate array, which is connected to the first programmable gate array to form a daisy chain.

Abstract: A method of reducing training data via a system having an encoder, wherein at least a portion of the training data forms a temporal sequence and is combined into a first set of training data, and the encoder maps input data to prototype feature vectors of a set of prototype feature vectors. A first input datum is received from the first set of training data, and propagated by the encoder. The input datum is assigned one or more feature vectors by the encoder, and depending on the assigned feature vectors, a defined set of prototype feature vectors is determined and assigned to the first input datum. An aggregated vector is created for the first input datum. A second aggregated vector is created for the second input datum and the first and second aggregated vectors are compared and a measure of similarity for the aggregated vectors is determined.

Abstract: A heat sink with a first sub-area and a second sub-area, designed for contacting a large area of a printed circuit board populated with electronic components. A thermal isolation extends between the first sub-area and the second sub-area, and a rigid mechanical connection that spans the thermal isolation connects the first sub-area to the second sub-area. As a result, the heat sink allows an assignment of sub-areas to electronic components on the printed circuit board, and contributes to mechanical stabilization of the printed circuit board.

Abstract: A computer-implemented method for restructuring a predefined distributed real-time simulation network, wherein the simulation network has a plurality of network nodes and a plurality of data connections, wherein each network node has at least one data connection interface for connecting a data connection, wherein the network nodes are at least partially in communication via the data connections, and wherein during operation of the simulation network a simulation application is executed on at least one network node. The method permits a structure for the real-time simulation network to be automatically found in which the critical communication connections are reduced and avoided as much as possible by determining the topology of the simulation network so that topology information concerning the network nodes and the data connections between the network nodes is available by determining expected values for node data rates or node latencies for the network nodes of the simulation network.

Abstract: A method is disclosed for synchronizing a checking apparatus, in which the checking apparatus is configured for testing at least one first electronic closed-loop control unit. Further disclosed is a checking apparatus which is transferable to a synchronized state. Additionally disclosed is a composite system which includes at least two checking apparatuses. Also disclosed are a checking apparatus for testing at least one first closed-loop control unit, and a composite system including at least one checking apparatus and a further checking apparatus, the latter checking apparatus being configured to have the same effect as the first checking apparatus.

Abstract: A module with a functional unit for generating a data stream with a data output for outputting the data stream to a serialization unit provided for receiving a data stream from a serialization unit of a first series. A serialization unit of a second series is set up to serialize the data stream and output it through the data output, and a configuration data input receives configuration data defining a first register configuration of a serialization unit. A mapping of register addresses of the serialization unit of the first series to register addresses of the serialization unit of the second series can be stored in a data memory of the module. The configuration unit is set up to read in the configuration data, to use the mapping, and to configure the registers of the serialization unit of the second series according to the configuration of the second register.

Abstract: A method for simulating different traffic situations for an autonomous or semiautonomous test vehicle. The method includes the simulated driving of the test vehicle through a simulated road network, and the simulated randomized driving of other vehicles through the simulated road network. The method also includes the capture of vehicle driving parameters. Further according to the method, there is a determination of whether a predefined traffic situation is satisfied by the test vehicle and at least one of the other vehicles, the at least one other vehicle being within a test zone around the test vehicle. Where the predefined traffic situation is satisfied, randomized driving of the at least one other vehicle can be stopped, and the at least one other vehicle can be made to perform a predetermined driving maneuver. The predetermined driving maneuver can provoke a reaction by the test vehicle.

Abstract: A computer-implemented method for integrating at least one signal value into a virtual control unit. The virtual control unit is executed on a simulation platform by means of a personal computer and requires at least one input signal, wherein at least one signal value can be assigned to the input signal. A simulation function provides at least one first simulated signal value to the virtual control unit. The microcontroller abstraction layer has a software component for integrating the first simulated signal value and a second external signal value into a virtual control unit, wherein the second external signal value is provided by an external peripheral device. A user makes a selection for the input signal via a user interface as to whether the software component is to use the first simulated signal value or the second external signal value.

Abstract: A method for planning the design of partitions for a programmable gate array comprising different types of logic blocks of predetermined position, and a plurality of program routines comprising at least one first program routine and at least one further program routine. A mapping of a first partition of the programmable gate array with the first program routine and at least one further partition of the programmable gate array with the at least one further program routine is performed. The need of the first program routine for the individual types of logic blocks is determined. Meeting this need with the logic block resources of corresponding type available in the first partition. At least one logic block of corresponding type from the further partition or at least one of the further partitions into the first partition is transferred.

Abstract: A method for monitoring message packets that are exchanged between at least two control units. The message packets are concatenated in a data stream and each have an identifier, a payload, and a length specification of the payload described by a data item of predefined word size. The at least two control units are connected by a distributor. The distributor is connected by a first distributor port to a first of the at least two control units, is connected by a second distributor port to a second of the at least two control units, and is connected by a third distributor port to a computer system. The data stream flows through the first and distributor port for communication between the first node and the second node. The computer system has a memory, and information on the respective identifiers of the message packets is stored in the memory.

Abstract: A modular computer system includes: a housing; at least one container; a data connection; and a housing cover. The at least one container in a lowered state is configured to be connected to a motherboard of the computer system via at least one data connection installed on the outside of the at least one container. The data connection is for exchanging data between pluggable circuit boards in the at least one container and the motherboard of the computer system while the at least one container is in the lowered state. The housing cover is configured to be fixed on the housing. A container holding device is installed on the housing cover, wherein the container holding device is configured to exert a force on the at least one container to fix the at least one container in a shakeproof manner in the housing after the housing cover has been fixed on the housing.

Abstract: A method for the usage-based licensing of one or more applications in a container, wherein the container comprises a license module, an application queries the presence of an application license via the license module and is only executed if an application license is present. In the license module, a linking of one or more application licenses with a unique identifier is stored, and the container comprises a settlement module, which retrieves a usage unit from an external license source. For the duration of an obtained usage unit, the settlement module provides the unique identifier in a secure data storage so that all applications linked with the unique identifier can be executed. A computer system and a computer program product are also provided.

Abstract: A method and replay unit for sending secured messages via a messaging system to a receiver ECU to be tested, wherein the replay unit is connected to the device under test via the messaging system, wherein the replay unit is set up to receive first secured messages to be replayed, to remove from the first secured messages a first counter value and a first authenticator, and to generate a second authenticator by means of a second counter value, an encryption algorithm and a key, and wherein the replay unit is set up to generate second secured messages by adding the second counter value and the second authenticator to the first messages, and wherein the replay unit is further adapted to send the second secured messages to the recipient device under test via the messaging system.

Abstract: A method for detecting errors of a first field-programmable gate array (FPGA) program includes: receiving, by a monitoring program executed on a processor connected to an FPGA on which the first FPGA program is executed, a signal value read out from the first FPGA program; and comparing, by the monitoring program executed on the processor, the signal value to a reference value from a source other than the first FPGA program in order to detect errors of the first FPGA program.

Abstract: A checking apparatus can test at least one first closed-loop control unit. The checking apparatus can include a first timing transmission unit which can generate a first periodic timing signal from a first time signal, and which can output the first periodic timing signal to a first PLL. The check device can further include a first oscillator which can generate a second periodic timing signal and which can output the second periodic timing signal to a second PLL. The checking device can additionally include a first clock, and can forward a first clock signal to a first input/output unit, and/or to a first computation unit. A first changeover signal can be used to control a first multiplexer such that depending on a state of the first changeover signal, the first multiplexer can forward either a first frequency-stabilized timing signal or a second frequency-stabilized timing signal to the first clock.

Abstract: A computer-implemented method for real-time simulation of the operation of a specific electric motor by a simulator arithmetic unit comprising a programmable logic device on which a generic motor model is implemented. The method includes: providing a generic system of equations corresponding to the generic motor model; receiving specific information corresponding to the specific motor to be simulated for the generic system of equations and inputting this information into the generic system of equations; generating a specific library containing at least some of the arithmetic operations required for the matrix operations for calculating the operation of the specific motor; implementing references in the generic motor model to the arithmetic operations of the specific library required for real-time simulation of the operation of the specific electric motor; and simulating the operation of the specific electric motor by running the generic motor model on the simulator arithmetic unit.

Abstract: To program a first programmable gate array, for example a first FPGA, in a distributed computer system, a configuration of a first configuration logic on the first programmable gate array is provided. The first configuration logic is configured to receive a first user bitstream from a configuration software for configuring a first user logic on the first programmable gate array and to store the first user bitstream on a non-volatile memory of the first programmable gate array for the purpose of subsequently configuring a first user logic on the first programmable gate array according to the specifications from the first user bitstream. In an expansion stage of the invention, a configuration of a programming logic on the first programmable gate array is also provided for programming a second programmable gate array, which is connected to the first programmable gate array to form a daisy chain.

Abstract: Source code is generated from one or a plurality of blocks of a block diagram. The block diagram is hierarchical and includes at least a first subsystem that is configured for an incremental code generation. The block diagram references a definition database which includes a first object. The method for generating the source code includes: opening, by a computer system, the block diagram including the first subsystem in a model editor; generating, by the computer system, source code for the first subsystem, wherein generating the source code for the first subsystem includes determining information about the first subsystem; storing, by the computer system, the information about the first subsystem in the first object; and generating, by the computer system, source code for the block diagram, wherein the first object is read out to influence at least one parameter for generating the source code for the block diagram.

Abstract: A computer-implemented method for simulating an electrical circuit via at least one computing unit, the electrical circuit comprising circuit components with switch elements, wherein the switch elements are capable of assuming either a conductive or a blocking switched state, wherein the circuit is described by a mathematical representation MR and the circuit for each total switched state is calculated on the computing unit by numerically solving the mathematical representation MR describing the total switched state.

Abstract: A method for planning the design of partitions for a programmable gate array comprising different types of logic blocks of predetermined position, and a plurality of program routines comprising at least one first program routine and at least one further program routine. A mapping of a first partition of the programmable gate array with the first program routine and at least one further partition of the programmable gate array with the at least one further program routine is performed. The need of the first program routine for the individual types of logic blocks is determined. Meeting this need with the logic block resources of corresponding type available in the first partition. At least one logic block of corresponding type from the further partition or at least one of the further partitions into the first partition is transferred.