Abstract: A virtual control unit according to the AUTOSAR standard, including a service layer, an ECU abstraction layer, and a microcontroller abstraction layer. It is provided according to invention that the virtual control unit additionally comprises a hardware layer that is configured to simulate at least one hardware component. A virtual control unit is provided in this way which enables easy use of environment models for HIL tests and software testing and a fast simulation.

Abstract: A computer-implemented method for implementing a V2X application on target hardware having a radio adapter, wherein the V2X application is modeled in the form of a block diagram by means of a graphical modeling environment and the block diagram is compiled into a V2X program that can be executed on the target hardware and the V2X program is transferred to the target hardware and executed there. The method for implementing a V2X application is realized in an especially simple and advantageous manner in that a V2X communication block that has at least one radio adapter interface, by means of which data are exchanged between the radio adapter and the V2X communication block, is used to create the block diagram.

Abstract: A method for regulating a volume flow rate, and a test stand with a liquid circuit for carrying out the method is provided. A pump and a flow control valve are connected in series in the liquid circuit, and the orifice width of the flow control valve is set as a function of a setpoint value of the volume flow rate of the liquid, in order to specify, on the basis of the orifice width, a characteristic curve of the pump that plots the volume flow rate over the differential pressure. Once a characteristic curve has been specified, the differential pressure of the pump is set such that the volume flow rate corresponds to the setpoint value of the volume flow rate.

Abstract: A method for visualizing system models in a model management environment, which includes the steps of opening the system model in the model editor, receiving a user input for rescaling a block, determining a relative horizontal position and a relative vertical position for each port in the block, calculating a new absolute horizontal and vertical position of each port in the block based on the relative horizontal and vertical position and the new size preset for the block, and displaying the block and each port in the block.

Abstract: A method and device for transmitting metrologically acquired and digitized measured data in a test device. The measured data corresponds to a program task, and a direction of the transmission of the measured data from a measured data transmitter of the test device is provided via a data channel to a measured data receiver of the test device. The measured data transmitter has a signal preprocessing processor, a task monitoring processor and a data channel arbiter. Via the task monitoring processor, a task ID data packet is generated at an execution start of the program task or at an execution end of the program task, and the task ID data packet is transmitted to the data channel arbiter. Via the data channel arbiter, the measured data and the task ID data packet are successively forwarded via the data channel as a data stream to the measuring data receiver.

Abstract: A configuration system for a test device designed for testing an electronic control unit. The test device is a hardware-in-the-loop simulator or a rapid control prototyping simulator, wherein a software model of a technical system is executed on the test device and the software model communicates electronically via an input/output interface of the test device with a system to be tested that is connected to the test device. Simulation data is electronically transmitted by the communication, and the configuration system is coupled to a modeling system and in the modeling system is a software model characterized by transversely and longitudinally connected function blocks. The configuration system configures the test device by interconnected configuration items such that the configuration items determine the physical characteristics of the input/output interface and/or the connection of the input/output interface with the software model.

Abstract: A method for generating an FPGA implementation based on an FPGA design serving as an FPGA model and/or a hardware description, including the steps of synthesizing a net list from the FPGA design and generating the FPGA implementation from the net list. The method includes searching for a similar FPGA implementation, the step of generating the FPGA implementation from the net list takes place using the similar FPGA implementation, the method includes a step of generating a graph-based representation based on the FPGA design, and the step of searching for a similar FPGA implementation comprises comparing the graph-based representation of the FPGA design with a graph-based representation of the at least one similar FPGA implementation. A method for generating a bit stream based on an FPGA design is also provided, serving as an FPGA model and/or a hardware description.

Abstract: A computer-implemented method for generating program code based on one or more blocks of a block diagram, at least one block including a block variable. The method comprises opening the block diagram in a model editor, retrieving generation settings for the block variable from a data definition tool, the generation settings comprising a scope of the variable, determining that a modification rule is referenced in the generation settings, and retrieving the referenced modification rule from the data definition tool, wherein a modification rule comprises a filter condition and one or more code changes. A processor generates program code based on the block diagram and the generation settings and applies the referenced modification rule to the block variable in the generated code, which includes verifying that the filter condition is fulfilled for the block variable and applying the code changes to each occurrence of the variable in the code.

Abstract: A method for operating a controller is provided. Program code having internal controller functions is stored on the controller, the program code being equipped with at least one service function. A service configuration for the at least one service function is provided on the controller. The method includes; detecting, in the controller, the service configuration; and executing a service functionality in accordance with the service configuration when the at least one service function is invoked. The service configuration denotes at least one internal controller function which is executed as a service functionality of the corresponding at least one service function. The at least one service function, via the service configuration, provides at least one value for at least one argument of the at least one internal controller function in the controller and/or receives at least one return value of the at least one internal controller function.

Abstract: A method for generating a documentation of a program, the program being generated from one or more blocks of a block diagram in a technical computing environment, the one or more blocks of the program having at least one hierarchical block whose functionality is defined by a plurality of blocks in a subordinate hierarchical level of the block diagram. The method is carried out by a computer system having at least one processor, the processor opening the block diagram at a top hierarchical level in a model editor of the technical computing environment and verifying if a documentation condition is fulfilled for the current hierarchical level of the block diagram. When the documentation condition is fulfilled, the processor generates documentation text for the blocks in the current hierarchical level.

Abstract: A method for generating an FPGA implementation based on an FPGA design serving as an FPGA model and/or a hardware description, including the steps of synthesizing a net list from the FPGA design and generating the FPGA implementation from the net list. The method includes searching for a similar FPGA implementation, the step of generating the FPGA implementation from the net list takes place using the similar FPGA implementation, the method includes a step of generating a graph-based representation based on the FPGA design, and the step of searching for a similar FPGA implementation comprises comparing the graph-based representation of the FPGA design with a graph-based representation of the at least one similar FPGA implementation. A method for generating a bit stream based on an FPGA design is also provided, serving as an FPGA model and/or a hardware description.

Abstract: A configuration system for a test device designed for testing an electronic control unit. The test device is a hardware-in-the-loop simulator or a rapid control prototyping simulator, wherein a software model of a technical system is executed on the test device and the software model communicates electronically via an input/output interface of the test device with a system to be tested that is connected to the test device. Simulation data is electronically transmitted by the communication, and the configuration system is coupled to a modeling system and in the modeling system is a software model characterized by transversely and longitudinally connected function blocks. The configuration system configures the test device by interconnected configuration items such that the configuration items determine the physical characteristics of the input/output interface and/or the connection of the input/output interface with the software model.

Abstract: A method for visualizing system models in a model management environment, which includes the steps of opening the system model in the model editor, receiving a user input for rescaling a block, determining a relative horizontal position and a relative vertical position for each port in the block, calculating a new absolute horizontal and vertical position of each port in the block based on the relative horizontal and vertical position and the new size preset for the block, and displaying the block and each port in the block.

Abstract: Computer network having a plurality of clocks that are synchronized with one another, that are distributed among multiple participants in the computer network, and from which a global system time of the computer network can be read out. The computer network includes a first synchronizing signal transmitter for a first synchronizing signal and a second synchronizing signal transmitter for a second synchronizing signal, and every participant can be equipped to synchronize the value of a locally stored variable quantity with a global value on the basis of the first synchronizing signal or the second synchronizing signal, and in doing so to take into account a time lag of the synchronizing signal.

Abstract: A method for simulating a peripheral circuit arrangement that can be connected to a control device is provided. A simulation device is electrically connected to the control device and has a first control element with which a first simulation current that can be passed from a first load terminal of the control device to a first control element output of the first control element can be influenced. The first control element includes a first multistage converter, and the simulation device also includes a first semiconductor switch control and a computing unit that executes model code. A first switch control signal is computed and provided for forwarding to the first semiconductor switch control, which has at least one first comparator. A pulse-width-modulated first gate-source voltage is generated and applied to a first control terminal and a first simulation current is influenced by the first gate-source voltage.

Abstract: A method for real-time testing of a control unit with a simulator is provided. The simulator calculates a load current and a load voltage as electrical load state variables via converter control data and via an electrical load model that does not take into account current discontinuities caused by the converter, and transmits at least a portion of the load state variables to the control unit. A control observer is additionally implemented on the simulator that calculates at least the load current as a load state variable taking into account the converter control data and an observer load model. The observer detects a zero-crossing of the load current and a current discontinuity caused thereby from the calculated load current, and upon detection of a current discontinuity the observer calculates an electrical compensating quantity.

Abstract: In a method for operating a process computer that is at least intermittently connected to a user computer that executes a configuration program that can transmit executable binary code to the process computer, there is provision for a license check. The binary code has associated license information that indicates required licenses, and the configuration program is set up to receive an explicit identification of the process computer. The configuration program supplies an authorization program with the identification and with the license information. The authorization program establishes a permissibility by checking whether the available licenses associated with the explicit identification cover the licenses required according to license information, and the configuration program transmits the executable binary code to the process computer only if the authorization program has established the permissibility. The disclosure further relates to a user computer and a computer program product.

Abstract: A method for emulating a three-phase, brushless DC motor using a load emulator that is connected in a three-phase manner via load terminals to supply terminals of a motor control unit. The load emulator has emulator power electronics and an emulator control unit for controlling the emulator power electronics. The emulator control unit determines the supply terminals that are actuated by the motor control unit and the supply terminals that are not actuated, and the emulator power electronics are actuated by the emulator control unit in such a way that phase currents calculated by the emulator control unit on the basis of a motor model flow in the supply terminals that are actuated by the motor control unit and a phase voltage calculated by the emulator control unit on the basis of a motor model is applied to the supply terminal that is not actuated by the motor control unit.

Abstract: A method for emulating a three-phase electric motor using a load emulator, wherein the load emulator is connected in a three-phase manner via its load terminals to the supply terminals of a motor controller. The load emulator has emulator power electronics and an emulator controller for controlling the emulator power electronics. The emulator controller determines the supply terminals that are driven by the motor controller and the supply terminals that are not driven. The emulator power electronics are driven by the emulator controller in such a manner that phase currents calculated by the emulator controller on the basis of a motor model flow in the supply terminals that are driven by the motor controller. A phase voltage calculated by the emulator controller on the basis of a motor model is applied to the supply terminal that is not driven by the motor controller.

Abstract: A test bench for a control system for controlling a wideband lambda sensor, which is configured to calculate an actual value, which represents an oxygen concentration in a measuring gap of a wideband lambda sensor or an indicator value from which the oxygen concentration can be derived, with consideration of a current generated by a pump voltage in an electrical circuit. In order to simulate the electrical response of a pump cell of the wideband lambda sensor, a first diode and a second diode are connected in parallel in the electrical circuit such that a current flows through the first diode at a first polarity of the pump voltage and a current flows through the second diode at a second polarity of the pump voltage.