Abstract: A method for generating a software component for an electronic control unit by a processor on a computer system, the software on the computer system comprising an architecture definition tool and a behavior-modeling tool, the architecture definition tool being adapted to define an architecture of the software component, architecture information comprising a declaration of one or more subcomponents and one or more interfaces, the architecture definition tool additionally being adapted to export and import architecture information, the behavior modeling tool being adapted to generate source code for the software component based on a function model comprising a plurality of interconnected blocks, the behavior-modeling tool additionally being adapted to import and export architecture information, wherein the behavior-modeling tool creates or updates a model framework for the function model based on the architecture information.

Abstract: A method for connecting models of technical systems in a testing device equipped for control unit development having a connection of a first model of a first technical system to a second model of a second technical system. The first model and the second model include a model of a control unit, a model of a technical system to be controlled, or a model of an environment interacting with the control unit or with the technical system to be controlled. The first model has a first data interface and the second model has a second data interface. The method has the provision of a first model hierarchy structure and the provision of a second model hierarchy structure. The method has an automatic configuration of compatible connections so that the first model present in the testing device exchanges data with the second model present in the testing device through compatible connections.

Abstract: A system composed of a function receive block and a function send block for a graphical, block-based modeling environment for graphical modeling of technical and mathematical relationships with a block diagram. Blocks of the block diagram have input ports and/or output ports, wherein the blocks can be connected through their ports by signal lines for data transmission. Especially flexible management of a functionality to be implemented is achieved in that the function receive block has a function receive port through which the function receive block can be assigned a functionality and only the interfaces of the assignable functionality are specified in the function receive block in the form of the number of inputs and/or the number of outputs of the functionality. The function send block has a function send port through which a functionality is sent out to an associated function receive block.

Abstract: A number of software routines comprising at least two software routines are created for an interface unit of a computer system having a first and a second interface processor for forwarding input data from a peripheral to a processor of the computer system on which software is programmed. A first subset of the software routines is assigned to a first category provided for task-synchronous data transfer, and a second subset of the software routines are assigned to a second category provided for continuous data transfer. The first interface processor is programmed with the first subset and the second interface processor with the second subset of software routines. During execution of the software, the first subset is cyclically executed by the first interface processor at a first cycle rate, and the second subset is cyclically executed by the second interface processor at a second cycle rate.

Abstract: A method in which the propagation times of a target network are simulated in an actual network, wherein the topology of the target network includes a number of senders and a number of receivers, and wherein the topology of the actual network includes one or more of the senders and receivers. A path between a first sender and a first receiver in the topology of the actual network differs from the path between the first sender and the first receiver in the topology of the target network, wherein in the actual network at least one first message of the first sender is received through a first network interface by a gateway having at least two network interfaces, is delayed by a delay, and is sent through a second network interface on a path to the first receiver.

Abstract: A method for generating an FPGA implementation based on an FPGA design serving as an FPGA model and/or a hardware description, including the steps of synthesizing a net list from the FPGA design and generating the FPGA implementation from the net list. The method includes searching for a similar FPGA implementation, the step of generating the FPGA implementation from the net list takes place using the similar FPGA implementation, the method includes a step of generating a graph-based representation based on the FPGA design, and the step of searching for a similar FPGA implementation comprises comparing the graph-based representation of the FPGA design with a graph-based representation of the at least one similar FPGA implementation. A method for generating a bit stream based on an FPGA design is also provided, serving as an FPGA model and/or a hardware description.

Abstract: A simulation apparatus for simulating a peripheral circuit arrangement connected to a regulating device and has a first current controller for influencing a first load current and a second current controller for influencing a first source current. The first current controller is controlled by a model code and used to set the first load current, and the first load current is routed to a first load connection of the regulating device. The second current controller is controlled by the model code and used to set the first source current, which is routed to a first supply connection of the regulating device. The model code influences the model code on the first current controller and the second current controller allows the first load current to be recovered at least proportionally from the first source current and/or the first source current to be recovered at least proportionally from the first load current.

Abstract: A configuration system for configuring a test system suitable for testing an electronic control unit, wherein a configuration diagram has a plurality of hierarchy elements, and a hierarchy element either has one hierarchy element or multiple hierarchy elements or no hierarchy element. The hierarchy element has an identifier, and wherein a hierarchy element has port(s) or no port, and wherein at least one hierarchy element is assigned to a functional property of the test system to be configured, wherein in an expanded view mode, the hierarchy elements are displayed at least partially nested and the ports and identifiers are shown one below the other, wherein in an at least partially collapsed view mode, a first set of hierarchy elements is shown such that the identifiers are shown side by side, wherein the ports and identifiers remain visible and the hierarchical relationship of the hierarchy elements remains displayed.

Abstract: A system for testing at least a first automatic control device via a plant model includes: a first subsystem; and a second subsystem which is spatially separated from the first subsystem. The plant model comprises an executable first model code and an executable second model code. The first subsystem comprises a first time-signal processing component configured to electronically assign a first time signal (Ts1) from a global time source to a first event. The first model code is configured to provide a first calculation result based on the first event. The second subsystem comprises a second time-signal processing component configured to electronically assign a second time signal (Ts2) from the global time source to a second event. The second model code is configured to provide a second calculation result based on the second event.

Abstract: A computer-implemented method for testing a control program that is modeled as one or more blocks of a block diagram in a computing environment. A first user interface is provided for selecting a simulation mode for the block diagram and a second user interface is provided for selecting a compiler intended for production code compilation. When it is confirmed that a software-in-the-loop simulation mode has been selected in the first user interface, the blocks of the block diagram are converted to a production code and is compiled to an executable using the compiler selected in the second user interface. By running the executable on the host computer while recording one or more data points based on input/output signals and/or evaluating the compliance of the one or more data points to one or more criteria, the control program corresponding to the one or more blocks is tested.

Abstract: The present disclosure relates to a method for generating an overall netlist (50) comprising the following steps: providing a first PLD code (24) as first netlist (26), wherein the first PLD code (24) has at least one first functional block (28), providing a second PLD code (30), wherein the second PLD code (30) has at least one second functional block (32) for alternative use instead of a corresponding first functional block (28), providing a switch PLD code (40) having at least one switch (42) assigned to the at least one first functional block (28) for connecting the first functional block (28) assigned to the switch (42), connecting the at least one second functional block (32) to one switch from the at least one switch (42) as an alternative to the corresponding first functional block (28), implementing at least one switch driving signal (44) for the at least one second functional block (32), wherein the at least one switch driving signal (44) is assigned to the corresponding switch (42) for connecting t

Abstract: A method for generating FPGA code based on an FPGA model with at least one signal value that is modeled as a constant. A constant is inserted with a predefined signal value in the FPGA model. A switching variable is set in the FPGA model for switching between a normal mode and a calibration mode for the FPGA code. The FPGA code is generated for the FPGA model having the implementation of the constants in the FPGA code, wherein the implementation of the constants when the switching variable is set for normal mode includes the implementation of the constants as a fixed value in the FPGA code, and the implementation of the constants when the switching variable is set for calibration mode includes the implementation of the constants as a modifiable signal value in the FPGA code. A method for calibrating an FPGA model is also provided.

Abstract: A method for changing a signal value of an FPGA at runtime, including the steps of loading an FPGA hardware configuration with at least one signal value onto the FPGA, running the FPGA hardware configuration on the FPGA, setting the signal value for transfer to the FPGA, determining writeback data from the signal value, writing the writeback data as status data to a configuration memory of the FPGA, and transferring the status data from the configuration memory to the functional level of the FPGA. A method is also provided for performing an FPGA build, including the steps of creating an FPGA hardware configuration with a plurality of signal values, arranging signal values in adjacent areas of the FPGA hardware configuration, ascertaining memory locations of a configuration memory for status data of the plurality of signal values on the basis of the FPGA hardware configuration, and creating a list containing signal values.

Abstract: A method for simulating a program modeled as one or more blocks of a block diagram in a technical computing environment. A block diagram is opened in a model editor. Source code is generated for the one or more blocks of the block diagram using the code generator. The program is configured from the source code using a predefined compiler in order to generate a binary executable file, and the program is simulated, which comprises running at least one function in the auxiliary file in order to determine at least the width of a basic data type corresponding to the enumeration variable in the binary executable file, and allocating one or more variables based on the determined byte width in order to log the simulation results.

Abstract: A method for simulating a program modeled as one or more blocks of a block diagram in a technical computing environment. A block diagram is opened in a model editor. Source code is generated for the one or more blocks of the block diagram using the code generator. The program is configured from the source code using a predefined compiler in order to generate a binary executable file, and the program is simulated, which comprises running at least one function in the auxiliary file in order to determine at least the width of a basic data type corresponding to the enumeration variable in the binary executable file, and allocating one or more variables based on the determined byte width in order to log the simulation results.

Abstract: A method for generating program code based on one or more blocks of a block diagram in a technical computing environment, an identifier being assigned to at least one, preferably each, of the one or more blocks of the block diagram. A processor opens the block diagram in the model editor, converts the block diagram to an intermediate representation using the code generator, wherein the conversion comprises checking if a replacement condition is fulfilled for a current block in the block diagram. Checking the replacement condition includes verifying that a predefined functional code unit is assigned to the identifier of the current block, in that case changing the block to a placeholder containing input/output-definitions but no functionality. The processor then converts the intermediate representation to program code, the conversion comprising adding a predefined functional code unit from the data definition tool to the definition code corresponding to the placeholder block.

Abstract: A method for operating a real-time-capable simulation network having multiple network nodes for computing a simulation model. The network nodes are connected to one another via a serial data bus, and the network nodes exchange data via data bus messages. At least one event-driven task of the simulation model is implemented on a first network node, and a nondeterministic triggering event is detected by a second network node. The second network node communicates the detected triggering event to the first network node and the first network node computes the event-driven task. A fast response time is achieved by the means that a detection signal is sent from the second network node in the form of a multicast data bus message or a broadcast data bus message to multiple network nodes of the simulation network or to all network nodes of the simulation network over the serial data bus.

Abstract: A configuration tool includes a tangible, non-transitory computer-readable medium having computer-executable instructions for configuring a model of a technical system and displaying the model on a display connected to a computer. The model includes at least two model components. Each model component has at least one port. Each model component is displayable in an expanded component representation on the display. The at least one port of each model component is connectable to at least one port of another model component by port association lines. Each model component is displayable in an expanded line representation on the display along with the at least one port and the port association lines of each model component. At least for one selected model component the port association lines connected to ports of the selected model component can be selected to be displayed in a reduced line representation.

Abstract: An input/output interface of a test device is configured, wherein the input/output interface is developed for connecting a hardware unit to a behavioral model present in the test device. The method includes the steps of: displaying a graphical representation of the input/output interface as a signal path between a hardware port for connection of the hardware and at least one model port for connecting the behavioral model via a selectable input/output function; receiving a first configuration for the signal path; receiving a test value that is predefinable at the hardware port or the model port of the signal path, but, for example, is also predefinable through the graphical representation of the hardware port or the model port; propagating a test signal associated with the test value along the signal path according to the first configuration for the signal path, and displaying the propagated test signal on the graphical representation of the model port or the hardware port.

Abstract: A method and a device for testing a control unit, in which sensor data are transmitted over a network connection to a real or simulated control unit, which data are calculated by a data processing system using simulation, in which the simulation of the sensor data takes place at least in part with at least one graphics processor of at least one graphics processor unit of the data processing system. The simulated sensor data are encoded in image data that are output via a visualization interface to a data conversion unit that simulates a visualization unit connected to the visualization interface. Via the data conversion unit the received image data are converted into packet data containing the sensor data through the network connection to the control unit.