Abstract: A power supplying circuit and an associated switch controller for a non-volatile memory are provided. When the sector erase is performed, the voltage stress withstood by the switching transistors in the power supplying circuit is lower than the maximum voltage stress. In addition, the voltage stress withstood by all transistors in the switch controller is lower than the maximum voltage stress. In other words, when the sector erase is performed, all switch controllers and all switching transistors in the power supplying circuit can be operated normally. In addition, an erase voltage is provided to a specified sector of the array structure, so that all memory cells in the specified sector are erased into the erase state.

Abstract: A memory device and a method for controlling a verification voltage of a memory device are provided. The method includes: determining a bit count of data bits verified in one verification cycle to be K according to electrical characteristics of a memory sector of the memory device, wherein K is a positive integer; controlling a charge pump circuit of the memory device to start detecting the verification voltage and start pulling up the verification voltage at a beginning time point of a present verification cycle of the memory sector; controlling the charge pump circuit to stop pulling up the verification voltage at a verification time point of the present verification cycle in response to the verification voltage reaching a predetermined level; and after the verification time point of the present verification cycle, using the verification voltage to verify K data bits written into the first memory sector.

Abstract: An antifuse-type non-volatile memory cell includes a select transistor, a following transistor and a capacitor. The first drain/source terminal of the select transistor is connected with a bit line. The gate terminal of the select transistor is connected with a word line. A first drain/source terminal of the following transistor is connected with a second drain/source terminal of the select transistor. A gate terminal of the following transistor is connected with a following line. A second drain/source terminal of the following transistor is connected with a first terminal of the capacitor. A second terminal of the capacitor is connected with an antifuse control line.

Abstract: A control gate voltage generating circuit for a non-volatile memory is provided. After the non-volatile memory leaves the factory, the control gate voltage is appropriately adjusted by the control gate voltage generating circuit according to the characteristics changes of the memory cells. When the read action is performed, the control gate voltage generating circuit provides the adjusted control gate voltage to the control gate line of the array structure. The magnitude of the reference current can be maintained in the range between the read current in the erase state and the read current in the program state. Consequently, the storage state of the selected memory cell can be accurately determined, and the life time of the non-volatile memory will be extended.

Abstract: A voltage selector includes a first input terminal for receiving a first input voltage, a second input terminal for receiving a second input voltage, an output terminal, a main select circuit and a reference circuit. The main select circuit includes a select unit for outputting a higher input voltage as an output voltage to the output terminal, and an auxiliary unit for pulling up the output voltage to the first input voltage according to a reference voltage when the first input voltage equals to the second input voltage. The reference circuit pulls up the reference voltage according to a higher one of the first input voltage and the second input voltage, and pulls down the reference voltage when the first input voltage equals to the second input voltage and the output voltage is lower than the first input voltage by a threshold voltage.

Abstract: A one-time-programmable (OTP) memory device includes a memory array including an N-type memory cell and a P-type memory cell. The N-type memory cell includes first channel layers and second channel layers. The P-type memory cell includes third channel layers and fourth channel layers. The N-type memory cell and the P-type memory cell further include a first word-line gate structure extending in the Y-direction and wrapping around the first channel layers and the third channel layers, and an anti-fuse gate structure extending in the Y-direction and wrapping around the second channel layers and the fourth channel layers. The OTP memory device further includes a wall structure extending in an X-direction and between the N-type memory cell and the P-type memory cell in the Y-direction. The first channel layers, the second channel layers, the third channel layers, and the fourth channel layers attach on the wall structure.

Abstract: A fault-injection protection circuit includes a circuit under protection and a detection circuit. The detection circuit includes a detection cell having unequal pull-up capability and pull-down capability, and is arranged at a distance less than a laser spot diameter from the circuit under protection. The detection circuit is used to generate an alarm signal upon detecting a laser fault injection.

Abstract: A control method for a non-volatile memory is provided. After the non-volatile memory is enabled, a judging step is performed to judge whether the non-volatile memory enters a read mode, a program mode or an erase mode. If the judging result indicates that the non-volatile memory enters the read mode, the program mode or the erase mode, a worst threshold voltage of plural reference cells of the non-volatile memory is searched. Then, at least one of a control voltage for read action, a control voltage for program verify and a control voltage for erase verify is determined. Then, a read action, a program action or an erase action is performed on plural data cells of the non-volatile memory.

Abstract: A non-volatile memory cell includes a p-type well region, a first n-type doped region, a second n-type doped region, a first gate structure, a second gate structure, a third gate structure and a protecting layer. The first n-type doped region and the second n-type doped region are formed under a surface of the p-type well region. The first gate structure and the second gate structure are formed over the surface of the p-type well region and arranged between the first n-type doped region and the second n-type doped region. A first part of a first gate layer of the first gate structure and the second gate structure are covered by the protecting layer. The third gate structure is formed over the surface of the p-type well region and arranged between the first gate structure and the second gate structure.

Abstract: A regulator includes a pre-regulator circuit, a pump circuit, an output stage circuit, and a tracking circuit. The pre-regulator circuit is configured to generate a pre-regulated voltage according to a power voltage. The pump circuit is configured to generate a pumped voltage according to the pre-regulated voltage and a tracking voltage. The output stage circuit is configured to generate an output voltage according to the pumped voltage and the power voltage. The tracking circuit is configured to track the output stage circuit to generate the tracking voltage and transmit the tracking voltage to the pump circuit.

Abstract: A non-volatile memory with an auxiliary select gate line driver is provided. The array structure of the non-volatile memory comprises plural 2T2C memory cells in an array arrangement. The memory cells in the array structure are connected with the corresponding auxiliary select gate lines. The auxiliary select gate line driver can output specified driving voltages to the auxiliary select gate lines. Consequently, the programming efficiency, the erasing efficiency and the reading efficiency of non-volatile memory are enhanced.

Abstract: A non-volatile memory cell includes a select transistor and a memory transistor. The first drain/source terminal of the select transistor is connected with a first control terminal. The second drain/source terminal of the select transistor is connected with the first drain/source terminal of the memory transistor. The gate terminal of the select transistor is connected with a select gate terminal. The second drain/source terminal of the memory transistor is connected with a second control terminal. The gate terminal of the memory transistor is connected with a memory gate terminal. During a program action, the select transistor is turned on, and a tapered channel is formed in the memory transistor. The tapered channel is pinched off near the first drain/source terminal of the memory transistor, and plural hot carriers near a pinch off point are injected into the charge storage layer.

Abstract: A sensing apparatus for a non-volatile memory includes two current mirrors, three switches, a voltage control circuit and a judging circuit. The input terminal of the first current mirror receives a reference current. A mirroring terminal of the first current mirror is connected with a data line. The first switch is connected between the data line and the voltage control circuit. The second switch is connected between the data line and a ground voltage. The third switch is connected between the voltage control circuit and a supply voltage. The input terminal of the second current mirror receives a bias current. The mirroring terminal of the second current mirror is connected with the judging node. The voltage control circuit and the judging circuit are connected with the judging node.

Abstract: A resistive memory cell includes a P-well region, an isolation structure, an N-well region, a first gate structure, a second gate structure, a first N-type doped region, a second N-type doped region, a third N-type doped region, a fourth N-type doped region, a word line, a bit line, a conductor line and a program line. The third N-type doped region, the fourth N-type doped region and the N-well region are collaboratively formed as an N-type merged region. The bit line is connected with the first N-type doped region. The word line is connected with a conductive layer of the first gate structure. The conductor line is connected with the second N-type doped region and a conductive layer of the second gate structure. The program line is connected with the N-type merged region.

Abstract: A memory cell of a charge-trapping non-volatile memory is provided. The memory cell is formed on a well region of a semiconductor substrate. The memory cell includes a storage transistor. A gate structure of the storage transistor includes a first tunneling layer, a second tunneling layer, a trapping layer, a blocking layer and a gate layer. The first tunneling layer is contacted with a surface of the well region. The second tunneling layer covers the first tunneling layer. The trapping layer covers the second tunneling layer. The blocking layer covers the trapping layer. The gate layer covers the blocking layer. The second tunneling layer has gradient nitrogen distribution. A first nitrogen concentration of a first region of the second tunneling layer close to the first tunneling layer is lower than a second nitrogen concentration of a second region of the second tunneling layer close to the trapping layer.

Abstract: A non-volatile memory receives a supply voltage. The non-volatile memory includes a reference current generator and a sensing circuit. The reference current generator provides a reference current to the sensing circuit. The reference current generator includes a control voltage generation circuit, a current path selecting circuit and a mirroring circuit. The control voltage generation circuit receives a control signal and generates a control voltage according to the control signal. The current path selecting circuit generates the reference current. A current input terminal of the mirroring circuit receives the reference current. If the control signal is set as a first value, the reference current is changed at a first slope in a range of the supply voltage. If the control signal is set as a second value, the reference current is changed at a second slope in the range of the supply voltage.

Abstract: An antifuse-type one time programming memory cell at least includes an antifuse transistor. The antifuse transistor includes a first nanowire, a first gate structure, a first drain/source structure and a second drain/source structure. The first nanowire is surrounded by the first gate structure. The first gate structure comprises a first spacer, a second spacer, a first gate dielectric layer and a first gate layer. The first drain/source structure is electrically contacted with a first terminal of the first nanowire. The second drain/source structure is electrically contacted with a second terminal of the first nanowire.

Abstract: A sense amplifier for a non-volatile memory is provided. A first memory cell of the non-volatile memory is coupled to a data line. The sense amplifier includes a first switching device, a first voltage boosting circuit and a comparator. A first terminal of the first switching device is connected with the data line. A second terminal of the first switching device is connected with a ground terminal. A control terminal of the first switching device receives a reset signal. An input terminal of the first voltage boosting circuit is connected with the data line. An output terminal of the first voltage boosting circuit is connected with a sensing node. A first input terminal of the comparator receives a comparison voltage. A second input terminal of the comparator is connected with the sensing node. An output terminal of the comparator generates an output data.

Abstract: A manufacturing method for a nonvolatile charge-trapping memory apparatus is provided. During the manufacturing process of the nonvolatile memory apparatus, a blocking layer of a storage device is effectively protected. Consequently, the blocking layer is not contaminated or thinned. Moreover, since the well regions of the logic device area and the memory device area are not simultaneously fabricated, it is feasible to fabricate small-sized nonvolatile memory cell in the memory device area and precisely control the threshold voltage of the charge trapping transistor.

Abstract: An OTP memory cell for a PUFF technology includes a first select transistor, a first antifuse transistor and a second antifuse transistor. A first drain/source terminal of the first select transistor is connected with a bit line. A gate terminal of the first select transistor is connected with a word line. A gate terminal of the first antifuse transistor is connected with a second drain/source terminal of the first select transistor. Two drain/source terminals of the first antifuse transistor are connected with a first antifuse control line. A gate terminal of the second antifuse transistor is connected with a second drain/source terminal of the first select transistor. Two drain/source terminals of the second antifuse transistor are connected with a second antifuse control line.